MC68LC302 Datasheet, PDF (72/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

DISC
15
14
13
12
11
TSTCLK1
TSRCLK1
BRGDIV
RESET:
0
0
0
0
0
7
6
5
4
3
RESET:
0
0
0
0
0
Communications Processor (CP)
Base+$8EE
10
9
8
0
0
0
2
1
0
0
0
0
4.3.2.1 RCLK1 AND TCLK1 PIN OPTIONS.
TSRCLK1
0 = RCLK1 is driven on its pin when SCC1 RCLK is the baud rate generator output.
1 = RCLK1 is three-state.
TSTCLK1
0 = TCLK1 is driven on its pin when SCC1 RCLK is the baud rate generator output.
1 = TCLK1 is three-state.
BRGDIV
Enables and disables the divide by two block between the TIN1 pin and the BRG1 pres-
caler input.
0 = The divide by two block is disabled.
1 = The divide by two block is enabled.
4.3.3 SCC Mode Register (SCM)
Each SCC has a mode register. The functions of bits 5–0 are common to each protocol. The
function of the specific mode bits varies according to the protocol selected by the MODE1–
MODE0 bits. They are described in the relevant sections for each protocol type. Each SCM
is a 16-bit, memory-mapped, read-write register. The SCMs are cleared by reset.
Only the Mode bits have changed functionality. For more information on the other bits,
please refer to the MC68302 Users’ Manual.
15
SPECIFIC MODE BITS
6
5
4
3
2
1
0
DIAG1 DIAG0 ENR ENT MODE1 MODE0
DIAG1–DIAG0—Diagnostic Mode
00 = Normal operation (CTS, CD lines under automatic control)
01 = Loopback mode
10 = Automatic echo
11 = Software operation
ENR— Enable Receiver
When ENR is set, the receiver is enabled. When it is cleared, the receiver is disabled, and
any data in the receive FIFO is lost. If ENR is cleared during data reception, the receiver
aborts the current character. ENR may be set or cleared regardless of whether serial
MOTOROLA
MC68LC302 REFERENCE MANUAL
4-5