MC68LC302 Datasheet, PDF (24/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
MF 11–0—Multiplication Factor
These bits define the multiplication factor that will be applied to the IMP PLL input frequen-
cy. The multiplication factor can be any integer from 1 to 4096. The system frequency is
((MF bits + 1) x EXTAL). The multiplication factor must be chosen to ensure that the re-
sulting VCO output frequency will be in the range from 10 MHz to the maximum allowed
clock input frequency (e.g. 20 MHz for a 20 MHz IMP).
The value 000 results in a multiplier value of 1. The value $FFF results in a multiplier value
of 4096.
Any time a new value is written into the MF11–MF0 bits, the IMP PLL will lose the lock
condition, and after a delay of 2500 EXTAL clocks, will relock. When the IMP PLL loses
its lock condition, all the clocks that are generated by the IMP PLL are disabled. After
hardware reset, the MF11–MF0 bits default to either 0, 3 or 400 ($190 hex) depending on
the MODCLK and VCCSYN pins (giving a multiplication factor of 1, 4 or 401). If the mul-
tiplication factor is 401, then a standard 32.768 kHz crystal generates an initial general
system clock of 13.14 MHz. If the multiplication factor is 4, then a standard 4.192 MHz
crystal generates an initial general system clock of 16.768 MHz. The user would then write
the MF bits or adjust the output frequency to the desired frequency.
NOTE
Since the clock source for the periodic interrupt timer is CLKIN
(see Figure 2-2), the PIT timer is not disturbed when the IMP
PLL is in the process of acquiring lock.
PEN—PLL Enable Bit
The PEN bit indicates whether the IMP PLL is operating. This bit is written by the
MC68LC302 based on the value of VCCSYN during reset. When the IMP PLL is disabled,
the VCO is not operating in order to minimize power consumption. During hardware reset
this bit is set if the VCCSYN pin specifies that the IMP PLL is enabled. The only way to
clear PEN is to hold the VCCSYN pin low during a hardware reset.
0 = The IMP PLL is disabled. Clocks are derived directly from the EXTAL pin.
1 = The IMP PLL is enabled. Clocks are derived from the CLKOUT output of the PLL.
CLKODM0–1—CLKO Drive Mode 0–1
These bits control the output buffer strength of the CLKO pin. Those bits can be dynami-
cally changed without generating spikes on the CLKO pin. Disabling CLKO will save pow-
er and reduce noise.
00 = Clock Out Enabled, Full-Strength Output Buffer.
01 = Clock Out Enabled, 2/3-Strength Output Buffer
10 = Clock Out Enabled, 1/3-Strength Output Buffer
11 = Clock Out Disabled (CLKO is driven high by internal pullup)
NOTE
These IMP bits are in a different address location than in the
MC68302, where they are located at address $FA (bits 15, 14).
MOTOROLA
MC68LC302 REFERENCE MANUAL
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