MC68LC302 Datasheet, PDF (14/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

SECTION 2
CONFIGURATION, CLOCKING, LOW POWER MODES,
AND INTERNAL MEMORY MAP
The MC68LC302 integrates a high-s/peed M68000 processor with multiple communications
peripherals. The provision of direct memory access (DMA) control and link layer manage-
ment with the serial ports allows high throughput of data for communications-intensive appli-
cations, such as basic rate Integrated Services Digital Network (ISDN).
The MC68LC302 can operate either in the full MC68000 mode with a 16-bit data bus or in
the MC68008 mode with an 8-bit data bus by connecting the bus width (BUSW) pin low.
NOTE
The BUSW pin is static and is not intended to be used for dy-
namic bus sizing. Instead the BSW and BSWEN bits in the BSR
register should be used to switch the bus width after reset (3.2
Programmable Data Bus Size Switch). If the state of the BUSW
pin is changed during operation of the MC68LC302, erratic op-
eration may occur.
Refer to the MC68000UM/AD, M68000 8-/16-/32-Bit Microprocessors User's Manual, and
the MC68302UM/AD, MC68302 Integrated Multiprotocol Processor User’s Manual, for com-
plete details of the on-chip microprocessor including the programming model and instruction
set summary. Throughout this manual, references may use the notation M68000, meaning
all devices belonging to this family of microprocessors, or the notation MC68000, MC68008,
meaning the specific microprocessor products.
This section is intended to describe configuration of the MC68LC302 and the differences
between theLC302 and the MC68000 and the MC68302.This section also includes tables
that show the registers of the IMP portion of the MC68LC302. All of the registers are memory
mapped into the 68000 space
2.1 MC68LC302 AND MC68302 SIGNAL DIFFERENCES
The MC68LC302 in CPU enable mode has Write Enable (WE) signals instead of UDS and
LDS signal. The Write Enable High (WEH/A0) signal indicates that most significant data byte
will be accessed, and the Write Enable Low (WEL/DS) indicates that the least significant
data byte will be accessed. When the core is disabled, WEH/A0 and WEL/DS become UDS/
A0 and LDS/DS respectively.
MOTOROLA
MC68LC302 REFERENCE MANUAL
2-1