MC68LC302 Datasheet, PDF (20/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
MULTIPLICATION FACTOR
(MF11–MF0)
DIVIDE FACTOR
(DF3–DF0)
Fast
Wake
Up
RINGO
EXTAL
PIN
XTAL
PIN
IMP
OSC.
CLKIN
IMP PLL
En
CLK OUT
MUX
VCO OUT
MUX
DIVIDE
BY 2
IMP SYSTEM
MUX ^CLOCK
(0 – Max
Operating Freq)
BRG
CLOCK
MUX
PIT CLOCK
Figure 2-2. MC68LC302 PLL Clock Generation Schematic
2.4.2.1 DEFAULT SYSTEM CLOCK GENERATION. During the assertion of hardware
reset, the value of the MODCLK and VCCSYN input pins determine the initial PLL settings
according to Table 2-2. After the deassertion of reset, these pins are ignored.
The MODCLK and VCCSYN pins control the IMP clock selection at hardware reset. The IMP
PLL can be enabled or disabled at reset only and the multiplication factor preset to support
different industry standard crystals. After reset, the multiplication factor can be changed in
the IPLCR register, and the IMP PLL divide factor can be set in the IOMCR register.
NOTE
The IMP input frequency ranges are limited to between 25 kHz
and the maximum operating frequency, and the PLL output fre-
quency range before the low power divider is limited to between
10 MHz and the maximum system clock frequency (25 MHz).
Table 2-2. Default System Clock Generation
CSelect
0
0
0
VCCSYN
MODCLK
0X
10
11
Example IMP
EXTAL Freq.
IMP PLL
25 MHz
Disabled
4.192 MHz Enabled
32.768 kHz Enabled
IMP
MF+1
IMP System Clock
x
IMP EXTAL
4
IMP EXTALx4
401 IMP EXTALx401
Note:
By loading the IPLCR register the user can change the multiplication factor of the PLL
after RESET.
By loading the IOMCR register, the user can change the power saving divide factor of
the IMP PLL.
MOTOROLA
MC68LC302 REFERENCE MANUAL
2-7