MC68LC302 Datasheet, PDF (27/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
sumption in STAND-BY mode is less than less than 5mA. The wake up time is a few IMP
system clock cycles.
The STAND_BY mode is entered by executing the STOP instruction with the LPM1–0 bits
in the IOMCR register set to 01. Refer to 2.4.4.2.2 Entering the STOP/ DOZE/ STAND_BY
Mode for an example instruction sequence for use with the STOP instruction.
2.4.4.1.4 SLOW_GO Mode. In the SLOW-GO mode, the IMP is fully operational but the
IMP PLL divider has been programmed with a value that is dividing the IMP PLL VCO output
to the system clock in order to save power. The PLL output divider can only be used with
the IMP PLL enabled. The divider value is programmed in the DF3–0 bits in the IOMCR. The
clock may be divided by a power of 2 (2⁰ – 2¹⁵). No functionality is lost in SLOW-GO mode.
2.4.4.1.5 NORMAL Mode. In NORMAL mode the IMP part is fully operational and the sys-
tem clock from the PLL is not being divided down.
2.4.4.1.6 IMP Operation Mode Control Register (IOMCR). IOMCR is a 8-bit read/ write
register used to control the operation modes of the IMP. The WP bit in IOMCR is used as a
protect mechanism to prevent erroneous writing of IOMCR.
IOMCR
$0FA
7
6
5
4
3
2
1
0
IOMWP
DF3
DF2
DF1
DF0
BCD
LPM1
LPM0
RESET:
0
0
0
0
0
0
0
0
Read/Write
IOMWP—IMP Operation Mode Control Write Protect Bit
This bit prevents accidental writing into the IOMCR. After reset, this bit defaults to zero to
enable writing. Setting this bit prevents further writing (excluding the first write that sets
this bit).
DF 3–0—Divide Factor
The Divide Factor Bits define the divide factor of the low power divider of the PLL. These
bits specify a divide range between 2⁰ and 2¹⁵. Changing the value of these bits will not
cause a loss of lock condition to the IMP PLL.
BCD—BRG Clock Divide Control
This bit controls whether the divide-by-two block shown in Figure 2-2 is enabled.
0 = The BRG clock is divided by 1.
1 = The BRG clock is divided by 2.
2-14
MC68LC302 REFERENCE MANUAL
MOTOROLA