MC68LC302 Datasheet, PDF (59/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
to the user as memory-mapped registers, may be read at any time. A bit is cleared by writing
a one to that bit (writing a zero does not affect a bit's value).
7
RESERVED
2
1
0
REF CAP
CAP—Capture Event
The counter value has been latched into the TCR. The CE bits in the TMR are used to
enable the interrupt request caused by this event.
REF—Output Reference Event
The counter has reached the TRR value. The ORI bit in the TMR is used to enable the
interrupt request caused by this event.
Bits 7–2—Reserved for future use.
3.7.3 Timer 3 - Software Watchdog Timer
A watchdog timer is used to protect against system failures by providing a means to escape
from unexpected input conditions, external events, or programming errors. Timer 3 may be
used for this purpose. Once started, the watchdog timer must be cleared by software on a
regular basis so that it never reaches its timeout value. Upon reaching the timeout value, the
assumption may be made that a system failure has occurred, and steps can be taken to re-
cover or reset the system. No changes have been made to the Software Watchdog Timer.
Please refer to the MC68302 Users’ Manual for more information.
3.7.3.1 Software Watchdog Reference Register (WRR)
WRR is a 16-bit register containing the reference value for the timeout. The EN bit of the
register enables the timer. WRR appears as a memory-mapped read-write register to the
user.
15
REFERENCE VALUE
1
0
EN
3.7.3.2 Software Watchdog Counter (WCN)
WCN, a 16-bit up-counter, appears as a memory-mapped register and may be read at any
time. Clearing EN in WRR causes the counter to be reset and disables the count operation.
A read cycle to WCN causes the current value of the timer to be read. A write cycle to WCN
causes the counter and prescaler to be reset. A write cycle should be executed on a regular
basis so that the watchdog timer is never allowed to reach the reference value during normal
program operation.
3.7.4 Periodic Interrupt Timer (PIT)
The MC68LC302 IMP provides a timer to generate periodic interrupts for use with a real-
time operating system or the application software. The periodic interrupt time period can
vary from 122 µs to 128 s (assuming a 32.768-kHz crystal is used to generate the general
system clock). This function can be disabled.
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MC68LC302 REFERENCE MANUAL
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