MC68LC302 Datasheet, PDF (141/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.13 AC ELECTRICAL SPECIFICATIONS—CHIP-SELECT TIMING
INTERNAL MASTER (see Figure 6-13)
Num.
150
151
152
153
154
155
158
171
172
173
174
175
176
177
178
Characteristic
Symbol
16.67 MHz
Min Max
Clock High to CS, IACK, OE, WEL, WEH
Low (see Note 2)
t_CHCSIAKL
0
40
Clock Low to CS, IACK, OE, WEL, WEH
High (see Note 2)
t_CLCSIAKH
0
40
CS Width Negated
t_CSH
60 —
Clock High to DTACK Low (0 Wait State) t_CHDTKL — 45
Clock Low to DTACK Low (1–6 Wait
States)
t_CLDTKL
—
30
Clock Low to DTACK High
t_CLDTKH
—
40
DTACK High to DTACK High Impedance t_DTKHDTKZ — 15
Input Data Hold Time from S6 Low
t_IDHCL
5—
CS Negated to Data-Out Invalid (Write)
t_CSNDOI
10
—
Address, FC Valid to CS Asserted
t_AFVCSA
15
—
CS Negated to Address, FC Invalid
t_CSNAFI
15
—
CS Low Time (0 Wait States)
t_CSLT
120 —
CS Negated to R/W Invalid
t_CSNRWI
10
—
CS Asserted to R/W Low (Write)
t_CSARWL —
10
CS Negated to Data-In Invalid (Hold Time
on Read)
t_CSNDII
0
—
20 MHz
Min Max
0 35
0 35
50 —
— 40
— 25
— 35
— 15
5—
10 —
15 —
15 —
100 —
10 —
— 10
0—
25 MHz
Min Max ^Unit
0 27 ns
0 27 ns
40 — ns
— 30 ns
— 20 ns
— 27 ns
— 27 ns
— 27 ns
— 10 ns
5 — ns
7 — ns
15 — ns
12 — ns
80 — ns
7 — ns
NOTE:
1. This specification is valid only when the ADCE or WPVE bits in the SCR are set.
2.For loading capacitance less than or equal to 50 pF, subtract 4 ns from the maximum value given.
3. Since AS and CS are asserted/negated on the same CLKO edges, no AS to CS relative timings can be
specified. However, CS timings are given relative to a number of other signals, in the same manner as
AS. See Figure 6-2 and Figure 6-3 for diagrams.
CLKO
(OUTPUT)
CS0–CS3
IACK1,IACK6,
IACK7
(OUTPUT)
DTACK
(OUTPUT)
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 Sw Sw S5 S6 S7 S0
152
150
151
153
155
154
158
Figure 6-13. Internal Master Chip-Select Timing Diagram
6-24
MC68LC302 REFERENCE MANUAL
MOTOROLA