MC68LC302 Datasheet, PDF (25/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
IPLWP—IMP PLL Control Write Protect Bit
This bit prevents accidental writing into the IPLCR. After reset, this bit defaults to zero to
enable writing. Setting this bit prevents further writing (excluding the first write that sets
this bit).
2.4.3.5 IMP INTERNAL CLOCK SIGNALS. The following paragraphs describe the IMP
internal clock signals.
2.4.3.5.1 IMP System Clock. The IMP system clock is supplied to all modules on the IMP
(with the exception of the BRG clocks which are connected directly to the VCO output with
the PLL enabled). The IMP can be programmed to operate with or without IMP PLL. If IMP
PLL is active, the system clock will be driven by PLL clock divider output. If IMP PLL is not
active, the system clock will be driven by the PLL input clock (CLKIN).
2.4.3.5.2 BRG Clock. The clock to the BRGs can be supplied from the IMP PLL input
(CLKIN) when the IMP PLL is disabled, or from the IMP PLL VCO output (when the PLL is
enabled). The BRG prescaler input clock may be optionally programmed to be divided by 2
to allow very low baud rates to be generated from the system clock by setting the BCD bit
in the IOMCR.
2.4.3.5.3 PIT Clock. CLKIN is supplied to the periodic interrupt timer (PIT) submodule
which allows the PIT clock to run independently of the system clock (refer to Figure 2-2 and
Section 3 System Integration Block (SIB)).
2.4.3.6 IMP PLL PINS. The following pins are dedicated to the IMP PLL operation.
2.4.3.6.1 VCCSYN. This pin is the V_CC dedicated to the analog IMP PLL circuits. The volt-
age should be well regulated, and the pin should be provided with an extremely low-imped-
ance path to the V_CC power rail if the PLL is to be enabled. VCCSYN should be bypassed
to GNDSYN by a 0.1-µF capacitor located as close as possible to the chip package.
VCCSYN should be tied to ground if the PLL is to be disabled.
2.4.3.6.2 GNDSYN. This pin is the GND dedicated to the analog IMP PLL circuits. The pin
should be provided with an extremely low-impedance path to ground. GDNSYN should be
bypassed to VCCSYN by a 0.1 µF capacitor located as close as possible to the chip pack-
age. The user should also bypass GNDSYN to VCCSYN with a 0.01 µF capacitor as close
as possible to the chip package.
2.4.3.6.3 XFC. This pin connects to the off-chip capacitor for the PLL filter. One terminal of
the capacitor is connected to XFC; the other terminal is connected to IQVCC.
2.4.3.6.4 MODCLK. MODCLK specifies what the initial VCO frequency is after a hardware
reset if VCCSYN is tied high. During the assertion of RESET, the value of the VCCSYN and
MODCLK input pins causes the PEN bit and the MF11–0 bits of the IMP PLL and Clock Con-
trol Register (IPLCR) $0F8 to be appropriately written.VCCSYN and MODCLK also deter-
mines if the oscillator’s prescaler is used. After RESET is negated, the MODCLK pins is
ignored and becomes PA12. Table 2-2 shows the combinations of VCCSYN and MODCLK
pins with the corresponding default settings.
2-12
MC68LC302 REFERENCE MANUAL
MOTOROLA