MC68LC302 Datasheet, PDF (18/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
Bits 11–0—Base Address
The high address field is contained in bit 11–0 of the BAR. These bits are used to set the
starting address of the dual-port RAM. The address compare logic uses only the most sig-
nificant bits to cause an address match within its block size. Even though A23-20 are sig-
nals are not available, they are driven internally by the core, or driven to zeroes in disable
CPU mode or when HALT has been asserted by an external master.
2.3 SYSTEM CONFIGURATION REGISTERS
A number of entries in the M68000 exception vectors table (located in low RAM) are
reserved for the addresses of system configuration registers (see Table 2-1). These regis-
ters have seven addresses within $0F0-$0FF. The MC68LC302 uses one of the IMP 32-bit
reserved spaces for 3 registers added for the MC68LC302. These registers are used to con-
trol the PLL, clock generation and low power modes. See 2.4 Clock Generation and Low
Power Control.
Address
$0F0
$0F2
$0F4
$0F7
$0F8
$0FA
$0FB
$0FC
Table 2-1. System Configuration Registers
Name
PITR
BAR
SCR
IWUCR
IPLCR
IOMCR
IPDR
RES
Width
16
16
24
8
16
8
8
32
Description
Periodic Interrupt Timer Register
Base Address Register
System Control Register
IMP Wake-Up Control Register
IMP PLL Control Register
IMP Operations Mode Control Register
IMP Power Down Register
Reserved
Reset Value
0000
BFFF
0000 0F
00
00
00
2.4 CLOCK GENERATION AND LOW POWER CONTROL
The MC68LC302 includes a clock circuit that consists of crystal oscillator drive circuit capa-
ble of driving either an external crystal or accepting an oscillator clock, a PLL clock synthe-
sizer capable of multiplying a low frequency clock or crystal such as a 32-kHz watch crystal
up to the maximum clock rate of each processor, and a low power divider which allows
dynamic gear down and gear up of the system clock for each processor on the fly.
• On-Chip Clock Synthesizers (with output system clocks)
—Oscillator Drive Circuits and Pins
—PLL Clock Synthesizer Circuits with Low Power Output Clock Divider Block.
• Low Power Control Of IMP
—Slow-Go Modes using PLL Clock Divider Blocks
—Varied Low Power STOP Modes for Optimizing Wake-Up Time to Low Power
Mode Power Consumption: Stand-By, Doze and STOP.
2.4.1 PLL and Oscillator Changes to IMP
The oscillator that was on the MC68302 has been replaced by the new clock synthesizer
described in this section.The registers related to the oscillator have been either removed or
MOTOROLA
MC68LC302 REFERENCE MANUAL
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