MC68LC302 Datasheet, PDF (58/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
ICLK—Input Clock Source for the Timer
00 = Stop count
01 = Master clock
10 = Master clock divided by 16
11 = Corresponding TIN pin, TIN1 or TIN2 (falling edge)
FRR—Free Run/Restart
0 = Free run—timer count continues to increment after the reference value is reached.
1 = Restart—timer count is reset immediately after the reference value is reached.
ORI—Output Reference Interrupt Enable
0 = Disable interrupt for reference reached
1 = Enable interrupt upon reaching the reference value
OM—Output Mode (Only available for Timer 1)
0 = Active-low pulse for one CLKO clock cycle (60 ns at 16.67 MHz)
1 = Toggle output
CE—Capture Edge and Enable Interrupt
00 = Capture function is disabled
01 = Capture on rising edge only and enable interrupt on capture event
10 = Capture on falling edge only and enable interrupt on capture event
11 = Capture on any edge and enable interrupt on capture event
PS—Prescaler Value
The prescaler is programmed to divide the clock input by values from 1 to 256. The value
00000000 divides the clock by 1; the value 11111111 divides the clock by 256.
3.7.2.2 Timer Reference Registers (TRR1, TRR2)
Each TRR is a 16-bit register containing the reference value for the timeout. TRR1 and
TRR2 are memory-mapped read-write registers.
3.7.2.3 Timer Capture Registers (TCR1, TCR2)
Each TCR is a 16-bit register used to latch the value of the counter during a capture opera-
tion when an edge occurs on the respective TIN1 or TIN2 pin. TCR1 and TCR2 appear as
memory-mapped read-only registers to the user.
3.7.2.4 Timer Counter (TCN1, TCN2)
TCN1 and TCN2 are 16-bit up-counters. Each is memory-mapped and can be read and writ-
ten by the user. A read cycle to TCN1 and TCN2 yields the current value of the timer and
does not affect the counting operation.
3.7.2.5 Timer Event Registers (TER1, TER2)
Each TER is an 8-bit register used to report events recognized by any of the timers. On rec-
ognition of an event, the timer will set the appropriate bit in the TER, regardless of the cor-
responding interrupt enable bits (ORI and CE) in the TMR. TER1 and TER2, which appear
MOTOROLA
MC68LC302 REFERENCE MANUAL
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