MC68LC302 Datasheet, PDF (164/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

G
GCI 4-2, 5-14, 5-15
SCIT 4-2
SIMASK 4-4
SIMODE 4-2
GCI See Signals
GIMR 3-14
GNDSYN 2-12, 5-5
H
HALT 2-4, 5-6
HALT See Signals
Hardware Watchdog 3-5
BERR 3-5, 3-6
HDLC
HDLC Event Register 4-21
HDLC Mask Register 4-21
HDLC Memory Map 4-20
HDLC Mode Register 4-20
Rx BD 4-21
SCCE 4-21
SCCM 4-21
Tx BD 4-21
HDLC Controller 4-20
HDLC Event Register 4-21
HDLC Mask Register 4-21
HDLC Memory Map 4-20
HDLC Mode Register 4-20
HDLC Receive Buffer Descriptor 4-21
HDLC Transmit Buffer Descriptor 4-21
I
IAC 5-10
IDL 4-2, 5-14, 5-15
SIMASK 4-4
SIMODE 4-2
IDL See Signals
IDMA (Independent DMA Controller)
DREQ 3-11
IMP Features
CP 1-2
IMP Operation Mode Control Register
(IOMCR) 2-14, 2-15
IMP PLL and Clock Control Register
(IPLCR) 2-10
IMP PLL Pins 2-12
Index
GNDSYN 2-12
MODCLK 2-12
VCCSYN 2-12
XFC 2-12
IMP System Clock Generation
IOMCR 2-8, 2-9, 2-10
IPLCR 2-8, 2-10
IMP System Clocks Schematic
PLL Disabled 2-8
IMP Wake-Up from Low Power STOP
Modes 2-17
IMR 3-16
Internal Loopback 4-3
Internal Registers 2-22
Internal Registers Map 2-23
Interrupt
Acknowledge 2-4
Control Pins 5-11
Controller 3-14
IPR 3-15
ISR 3-16
Interrupt Control Pins 5-11
Interrupt Controller 3-14
IOMCR 2-7, 2-14, 2-16
IPL 5-11
IPL0 5-11
IPL1 5-11
IPL2 5-11
IPL2-IPL0 5-11
IPLCR 2-7, 2-10
IPR 3-15
IPWRD 2-15
IRQ1 5-12
ISDN 5-14
ISR 3-16
IWUCR 2-17
L
Loopback Control 4-3
Loopback Mode
Internal Loopback 4-3
Loopback Control 4-3
Loopback mode 4-5
Low Power 2-13
68000 bus 2-13
Low Power Drive Control Register 2-13
Low Power Drive Control Register (LPDCR)
MOTOROLA
MC68LC302 REFERENCE MANUAL
INDEX-3