MC68LC302 Datasheet, PDF (38/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

SECTION 3
SYSTEM INTEGRATION BLOCK (SIB)
The MC68LC302 contains an extensive SIB that simplifies the job of both the hardware and
software designer. Most of the features are taken from the MC68302 without change, fea-
tures that have been added are highlighted in bold text.
NOTE
This section will only present the register descriptions for each
block. For more information on the operation of each block,
please refer to the MC68302 Users’ Manual. Items that are new
or have changed will be described in detail.
The SIB includes the following functions:
• IDMA Controller
• Interrupt Controller with Two Modes of Operation
• Parallel Input/Output (I/O) Ports, Some with Interrupt Capability
• Parallel Input/Output Ports on D15-D8 in 8 bit mode
• On-Chip 1152-Byte Dual-Port RAM
• Four Timers Including a Watchdog Timer and Periodic Interrupt Timer
• Four Programmable Chip-Select Lines with Wait-State Generator Logic
• Glueless Interface to SRAM, EPROM, Flash EPROM, and EEPROM
• System Control
—System Status and Control Logic
—Disable CPU Logic (M68000)
—Bus Arbitration Logic with Low-Interrupt Latency Support (for internal DMA)
—Hardware Watchdog for Monitoring Bus Activity
—DRAM Refresh Controller
—Programmable Bus Width
• Boot from SCC
3.1 SYSTEM CONTROL
The IMP system functions are configured using the System Control Register (SCR). The fol-
lowing systems are configurated:
• System Status and Control Logic
MOTOROLA
MC68LC302 REFERENCE MANUAL
3-1