MC68LC302 Datasheet, PDF (43/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
HWDCN–HWDCN0—Hardware Watchdog Count 2–0
000 = an internal BERR is asserted after 128 clock cycles (8 µs, 16-MHz clock)
001 = an internal BERR is asserted after 256 clock cycles (16 µs, 16-MHz clock)
010 = an internal BERR is asserted after 512 clock cycles (32 µs, 16-MHz clock)
011 = an internal BERR is asserted after 1K clock cycles (64 µs, 16-MHz clock)
100 = an internal BERR is asserted after 2K clock cycles (128 µs, 16-MHz clock)
101 = an internal BERR is asserted after 4K clock cycles (256 µs, 16-MHz clock)
110 = an internal BERR is asserted after 8K clock cycles (512 µs, 16-MHz clock)
111 = an internal BERR is asserted after 16K clock cycles (1 ms, 16-MHz clock)
3.2 PROGRAMMABLE DATA BUS SIZE SWITCH
The following procedure allows 68LC302 to be booted in an 8 or 16 bit bus width and then
switched to 16 or 8 bit bus width for future accesses. It does not implement true dynamic
bus sizing, but allows a software reconfiguration of the BUSW pin.
3.2.1 Bus Switch Register (BSR)
BSR
7
0
0
6
BSW
0
5
BSWEN
0
Base +$82C
4
3-0
0
0
0
0
BWSEN - Bus Width Switch Enable
When this bit is toggled from a zero to a one, the bus width switch mechanism is enabled.
From the point this bit is toggled, the bus width is determined by the BSW bit of this reg-
ister. If another bus width switch is necessary, this bit must be toggled back to zero and
then one again.
Setting this bit implements a hardware state machine that arbitrates the internal bus away
from the 302 core, changes the BUSW pin internally, and then gives the bus back to the
302 core.
BUSW - Bus Width
This bit determines the bus width after the bus width switch is performed.
0 - Data bus width is 8 bits
1 - Data bus width is 16 bits.
3.2.2 Basic Procedure:
The MC68LC302 is booted in its 8-bit mode by externally connecting the BUSW pin to GND.
It is expected that the MC68LC302 will be executing out of EPROM or flash at this time, and
that no external data memory is available in 8-bit mode.
The MC68LC302 initializes the BAR register to place the 4K block of dual-port RAM and
peripherals in an area that does not overlap the EPROM region. Note that this is part of a
normal 302 initialization sequence. Also note that the CFC bit of the BAR register should
NOT be set -- it must be cleared.
3-6
MC68LC302 REFERENCE MANUAL
MOTOROLA