MC68LC302 Datasheet, PDF (41/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
BG, regardless of the M68000 core RMC. If an IMP chip select is used then the
DTACK generator will insert wait states on the read cycle only.
1 = The IMP uses the internal RMC to negate AS and CS at the end of the read portion
of the RMC cycle and reasserts AS and CS at the beginning of the write portion.
BG will not be asserted until the end of the write portion. If an IMP chip select is
used, the DTACK generator will insert wait states on both the read and write portion
of the cycles.
The assertion of the internal RMC by the M68000 core is seen by the arbiter and will pre-
vent the arbiter from issuing bus grants until the completion of M68000-initiated locked
read-modify-write activity. After system reset, this bit defaults to zero.
EMWS—External Master Wait State (EMWS) (VALID only in Disable CPU Mode)
When EMWS is set and an external master is using the chip-select logic for DTACK gen-
eration or is synchronously reading from the internal peripherals (SAM = 1), one additional
wait state will be inserted in every memory cycle to external memory, peripherals, and al-
so, in every cycle to internal memory and peripherals. When EMWS is cleared, all syn-
chronous internal accesses will be with zero wait states and the chip-select logic will
generate DTACK after the exact programmed number of wait states. The chip-select lines
are asserted slightly earlier for internal master memory cycles than for an external master.
EMWS should be set whenever these timing differences will necessitate an additional wait
state for external masters. After system reset, this bit defaults to zero.
ADCE—Address Decode Conflict Enable
0 = an internal BERR is not asserted by a conflict in the chip-select logic when two or
more chip-select lines are programmed to overlap the same area.
1 = an internal BERR is asserted by a conflict in the chip-select logic when two or more
chip-select lines are programmed to overlap the same area.
BCLM—Bus Clear Mask
0 = The arbiter does not use the M68000 core internal IPEND signal to assert the in-
ternal bus clear signals.
1 = The arbiter uses the M68000 core internal IPEND signal to assert the internal bus
clear signals.
SAM—Synchronous Access Mode (Valid only in Disable CPU Mode)
This bit controls how external masters may access the IMP peripheral area. This bit is not
relevant for applications that do not have external bus masters that access the IMP. In ap-
plications such as disable CPU mode, in which the M68000 core is not operating, the user
should note that SAM may be changed by an external master on the first access of the
IMP, but that first write access must be asynchronous with three wait states. (If DTACK is
used to terminate bus cycles, this change need not influence hardware.)
0 = Asynchronous accesses. All accesses to the IMP internal RAM and registers (in-
cluding BAR and SCR) by an external master are asynchronous to the IMP clock.
Read and write accesses are with three wait states, and DTACK is asserted by the
IMP assuming three wait-state accesses. This is the default value.
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MC68LC302 REFERENCE MANUAL
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