MC68LC302 Datasheet, PDF (118/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

SECTION 6
ELECTRICAL CHARACTERISTICS
The AC specifications presented consist of output delays, input setup and hold times, and
signal skew times. All signals are specified relative to an appropriate edge of the clock
(CLKO pin) and possibly to one or more other signals. The timing for the LC302 signals is
the same as the corresponding signals of the 68302.
VERY IMPORTANT NOTE REGARDING SIGNALS
A few signals have been added to and removed from the
68LC302 or their functionality has changed. Several signals are
only available when 68302 is in CPU disable mode.The IAC,
FC2-FC0, AVEC and FRZ signals are only available on the PGA
package. The A23-A20, RMC, BERR, BCLR, IACK1, IACK6,
IACK7, DREQ, DACK, DONE, BRG1, TOUT1, NC1, NC3,
TCLK3, RTS3, CTS3, CD3 signals have been removed UDS,
LDS, R/W, BR, BG, BGACK are available only in Slave Mode.
The following diagrams and tables show the timing for all avail-
able signals. For complete information on which signals are
available in which modes (CPU disable), please refer to Section
5 of this Addendum.
MOTOROLA
MC68LC302 REFERENCE MANUAL
6-1