MC68LC302 Datasheet, PDF (54/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
15
14
13
12
11
10
9
8
PB11
PB10
SCC1
SDMA
IDMA
SCC2
TIMER1
0
7
6
5
4
3
2
1
0
PB9
TIMER2
SCP
TIMER3
SMC1
SMC2
PB8
0
3.6 PARALLEL I/O PORTS
The IMP supports three general-purpose I/O ports, port A, port B, and port N, whose pins
can be general-purpose I/O pins or dedicated peripheral interface pins. Some port B pins
are always maintained as four general-purpose I/O pins, each with interrupt capability.
3.6.1 PARALLEL I/O PORT DIFFERENCES
The following port pins were removed: PA11, PA13, PA14, PA15, PB0, PB1, PB2, and PB4.
If these signals are programmed to be inputs, the corresponding values in the data registers
will be indeterminate. If these pins are programmed to be output, then the output value will
be read back in the data register.
The SCP pins are now multiplexed onto PA8, PA9, and PA10.
The MODCLK pin is multiplexed with the PA12 port pin. After reset, this pin becomes a gen-
eral purpose I/O pin.
An 8-bit port, Port N, has been added. Port N is only available when the MC68LC302 is in
8-bit mode (internal BUSW=0).
3.6.2 Port A
Each of the port A pins are independently configured as a general-purpose I/O pin if the cor-
responding port A control register (PACNT) bit is cleared. Port A pins are configured as ded-
icated on-chip peripheral pins if the corresponding PACNT bit is set.When acting as a
general-purpose I/O pin, the signal direction for that pin is determined by the corresponding
control bit in the port A data direction register (PADDR). The port I/O pin is configured as an
input if the corresponding PADDR bit is cleared; it is configured as an output if the corre-
sponding PADDR bit is set. The PADAT register is used to read and write values for the Port
A pins. All PACNT bits and PADDR bits are cleared on total system reset, configuring all
port A pins as general-purpose input pins.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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