MC68LC302 Datasheet, PDF (167/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Index
DREQ 3-11
DTACK 3-4, 3-26, 3-28, 5-12
EXTAL 5-2, 5-4
FC2-FC0 5-12
GCI 5-15
HALT 2-4, 5-6
IAC 5-10
IDL 5-15, 5-17
ILP0 5-11
IRQ1 5-12
NMSI2 5-17
NMSI3 5-18
PCM Highway 5-15
Port A 5-17, 5-18
Port B 5-20
RESET 2-3, 5-6, 5-20
RMC 3-4
RTS1 5-17
SCP 5-19
TIN1/TIN2 5-20
WDOG 3-18, 5-20
XTAL 5-4
SIMASK 4-2, 4-4
SIMODE 4-2
SLOW_GO 2-10, 2-13, 2-14, 2-15
SLOW_GO Mode 2-14
SMC 2-20
Serial Management Controllers 4-26
SMC Memory Structure 4-26
Software Operation 4-5
Software Watchdog Timer 3-22
STAND_BY 2-13, 2-16
STAND_BY Mode 2-13
STOP 2-13, 2-16
STOP Mode 2-13
Supervisor
Data Space 2-3
System Control Registers (SCR) 2-4
System Clock
IMP 2-12
System Control 3-1
System Control Bits 3-3
System Control Pins 5-5
System Control Register (SCR) 3-2
System Status Bits 3-3
T
TCLK1
Disabling 4-5
TCLK1/L1SY0/SDS1 5-16
TCN1, TCN2 3-21
TCR1, TCR2 3-21
TER1, TER2 3-21
Thermal Characteristics 6-2
Timer
PIT 3-22
Timer Pins 5-19
Timers 3-20
TIN1/TIN2 5-20
WDOG 3-18, 3-22
TIN1/TIN2 5-20
TIN1/TIN2 See SCC
TMR1, TMR2 3-20
Transparent Controller 4-23
Transparent Event Register 4-25
Transparent Mask Register 4-25
Transparent Mode Register 4-24
Transparent Receive Buffer Descriptor
4-24
Transparent Transmit Buffer Descriptor
4-25
TRR1, TRR2 3-21
TTL Levels 5-2
TXD1/L1TXD 5-15
U
UART Controller 4-7
UART Event Register 4-9
UART Mask Register 4-9
UART Memory Map 4-7
UART Mode Register 4-8
UART Receive Buffer Descriptor 4-8
UART Transmit Buffer Descriptor 4-8
V
VCCSYN 2-12, 5-5
VCO 2-10, 2-11
Vector Generation Enable 3-5
W
Wake_Up
Clock cycles, IMP 2-13
INDEX-6
MC68LC302 REFERENCE MANUAL
MOTOROLA