MC68LC302 Datasheet, PDF (39/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
• AS Control During Read-Modify-Write-Cycles
• Disable CPU (M68000) Logic
• Bus Arbitration Logic with Low-Interrupt Latency Support (Disable CPU only)
• Hardware Watchdog
• Low-Power (Standby) Modes
• Freeze Control (Only supported in the PGA package)
3.1.1 System Control Register (SCR)
The SCR is a 32-bit register that consists of system status, control bits, a bus arbiter control
bit, and hardware watchdog control bits. Refer to Figure 3-1 and to the following paragraphs
for a description of each bit in this register. The SCR is a memory-mapped read-write regis-
ter. The address of this register is fixed at $0F4 in supervisor data space (FC = 5).
$F4
31
30
29
28
27
26
25
24
Res
0
0
0
I IPA
HWT WPV ADC
$F5
23
22
21
20
19
18
17
16
RME ERRE VGE WPVE RMCST EMWS ADCE BCLM
$F6
15
14
13
12
11
10
9
8
FRZW FRZ2 FRZ1 SAM HWDEN
HWDCN2–HWDCN0
Figure 3-1. System Control Register
Table 3-1. SCR Register Bits
Bit
IPA
HWT
WPV
ADC
RME
ERRE
VGE
WPVE
RMCST
EMWS
ADCE
BCLM
FRZW
FRZ1
FRZ2
SAM
HWDEN
HWDCN
Name
Interrupt Priority Active
Hardware Watchdog Timeout
Write Protect Violation
Address Decode Conflict
Ram Microcode Enable
External RISC Request Enable
Vector Generation Enable
Write Protect Violation Enable
Read-Modify-Write Cycle Special Treatment
External Master Wait State
Address Decode Conflict Enable
Bus Clear Mask
Freeze Watch Dog Timer Enable
Freeze Timer 1 Enable
Freeze Timer 2 Enable
Synchronous Access Mode
Hardware Watchdog Enable
Hardware Watchdog Count
3-2
MC68LC302 REFERENCE MANUAL
MOTOROLA