MC68LC302 Datasheet, PDF (16/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
The BAR entry contains the BAR described in this section. The SCR entry contains the SCR
described in Section 3 System Integration Block (SIB).
Figure 2-1 shows all the IMP on-chip addressable locations and how they are mapped into
system memory.
IMP
$0F0
PITR
SYSTEM MEMORY MAP
$0
EXCEPTION
VECTOR
TABLE
$0F2
BAR ENTRY
$0F4 SCR ENTRY
$0F7
WAKE-UP
256 VECTOR
ENTRIES
$3FF
$0F8
IMP PLL
$0FA IMP MODE CONTROL
$0FB _{IMP POWER DOWN}
BAR
POINTS
TO THE
BASE
BASE + $0
4K BLOCK
SYSTEM RAM
(DUAL-PORT)
BASE + $400
PARAMETER RAM
(DUAL-PORT)
$xxx000 = BASE
4K BLOCK
BASE + $800
BASE + $FFF
INTERNAL
REGISTERS
$FFFFFF
Figure 2-1. IMP Configuration Control
The on-chip peripherals, including those peripherals in both the communications processor
(CP) and system integration block (SIB), require a 4K-byte block of address space. This 4K-
byte block location is determined by writing the intended base address to the BAR in super-
visor data space (FC = 5). The FC2-0 pins are internally driven by the MC68LC302 to super-
visor data space.
After a total system reset, the on-chip peripheral base address is undefined, and it is not
possible to access the on-chip peripherals at any address until BAR is written. The BAR and
the SCR can always be accessed at their fixed addresses.
NOTE
The BAR and SCR registers are internally reset only when a to-
tal system reset occurs by the simultaneous assertion of RESET
MOTOROLA
MC68LC302 REFERENCE MANUAL
2-3