MC68LC302 Datasheet, PDF (22/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
MHz. Additionally, the system clock frequency can be driven directly onto the EXTAL pin. In
this case, the EXTAL frequency should be the exact system frequency desired (0 to Maxi-
mum Operating Frequency) and the XTAL pin should be left floating. Figure 2-4 shows all
the external connections required for the on-chip oscillator (as well as the PLL, VCC, and
GND connection
VCC
~390pf x MF 0.1µF
CRYSTAL
20pf
EXTAL
20pf
20M
XTAL XFC
VCCSYN
0.01µF
GNDSYN
CRYSTAL
OSCILLATOR
CLOCK GENERATION
VCC
ICLVCC
ICLGND
CLKO
0.1µF
Figure 2-4. PLL External Components
2.4.3.3 PHASE-LOCKED LOOP (PLL). The IMP PLL’s main function is frequency multipli-
cation. The phase-locked loop takes the CLKIN frequency and outputs a high-frequency
source used to derive the general system frequency of the IMP. The IMP PLL is comprised
of a phase detector, loop filter, voltage-controlled oscillator (VCO), and multiplication block.
2.4.3.4 FREQUENCY MULTIPLICATION. The IMP PLL can multiply the CLKIN input fre-
quency by any integer between 1 and 4096. The multiplication factor may be changed to the
desired value by writing the MF11–MF0 bits in the IPLCR. When the IMP PLL multiplier is
modified in software, the IMP PLL will lose lock, and the clocking of the IMP will stop until
lock is regained (worst case is 2500 EXTAL clocks). If an alteration in the system clock rate
is desired without losing IMP PLL lock, the value in the low-power clock divider can be to
modified to lower the system clock rate dynamically. The low power clock divider bits are
located in the IOMCR register.
NOTE
If IMP PLL is enabled, the multiplication value must be large
enough to result in the VCO clock being greater than 10 MHz.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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