MC68LC302 Datasheet, PDF (64/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
Bits 15–12—DTACK Field
These bits are used to determine whether DTACK is generated internally with a program-
mable number of wait states or externally by the peripheral.
Table 3-4. DTACK Field Encoding
Bits
15
14
13
Description
0
0
0
No Wait State
0
0
1
1 Wait State
0
1
0
2 Wait States
0
1
1
3 Wait States
1
0
0
4 Wait States
1
0
1
5 Wait States
1
1
0
6 Wait States
1
1
1
External DTACK
Bits 12–2—Base Address Mask
These bits are used to set the block size of a particular chip-select line. The address com-
pare logic uses only the address bits that are not masked (i.e., mask bit set to one) to de-
tect an address match.
0 = The address bit in the corresponding BR is masked.
1 = The address bit in the corresponding BR is not masked.
MRW—Mask Read/Write
0 = The RW bit in the BR is masked.
1 = The RW bit in the BR is not masked.
NOTE
For correct operation of the CS logic, MRW bit cannot be set in
Slave Mode or in systems where an External Master can take
ownership of the Bus.
CFC—Compare Function Code
0 = The FC bits in the BR are ignored.
1 = The FC bits on the BR are compared.
NOTE
Compare Function Code may be useful in systems where only
Internal Masters (CPU or DMA) take ownership of the Bus be-
cause those masters drive the FC2-0 signals internally. In Slave
Mode or in systems where External Masters take ownership of
the bus, CFC should be programmed to 0.
MOTOROLA
MC68LC302 REFERENCE MANUAL
3-27