MC68LC302 Datasheet, PDF (23/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
2.4.3.4.1 Low Power PLL Clock Divider. The output of the IMP VCO is sent to a low
power divider block. The clock divider can divide the output frequency of the VCO before it
generates the system clock. The clock for the baud rate generators (BRGs) bypasses this
clock divider.
The purpose of the clock divider is to allow the user to reduce and restore the operating fre-
quency of the IMP without losing the IMP’s PLL lock. Using the clock divider, the user can
still obtain full IMP operation, but at a slower frequency. The BRG is not affected by the low
power divider circuitry so previous BRG divider settings will not have to be changed when
the divide factors are changed.
When the PLL low power divider bits (DF0–3) are programmed to a non-zero value, the IMP
is in SLOW_GO mode. The selection and speed of the SLOW_GO mode may be changed
at any time, with changes occurring immediately.
NOTE
The IMP low power clock divider is active only if the IMP PLL is
active.
The low-power divider block is controlled in the IOMCR. The default state of the low-power
divider is to divide all clocks by 1.
If the low-power divider block is not used and the user is concerned that errant software
could accidentally write the IOMCR, the user may set a write protection bit in IOMCR to pre-
vent further writes to the register.
2.4.3.4.2 IMP PLL and Clock Control Register (IPLCR). IPLCR is a 16-bit read/write reg-
ister used to control the IMP’s PLL, multiplication factor and CLKO drive strength. This reg-
ister is mapped in the 68000 bus space at address $0F8. If the 68000 bus is set to 8 bits
(BUSW grounded at reset), during 8-bit accesses, changes to the IPLCR will take effect in
the IMP PLL after loading the high byte of IPLCR (the low byte is written first). The WP bit
in IPLCR is used as a protect mechanism to prevent erroneous writing. When this bit is set
further accesses to the IPLCR will be blocked.
IMP PLL and Clock Control Register (IPLCR)
$0F8
15
IPLWP
RESET
0
14
13
CLKOMOD0–1
0
0
12
PEN
VCCSYN
11
MF11
0
10
MF10
0
9
8
MF9
MF8
0
VCCSYN/MODCLK
7
6
MF7
MF6
RESET
VCCSYN/MODCLK1
0
Read/Write
2-10
5
4
3
MF5
MF4
MF3
0
VCCSYN/MODCLK
0
2
1
0
MF2
MF1
MF0
0
MODCLK
MODCLK
MC68LC302 REFERENCE MANUAL
MOTOROLA