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MC68LC302 Datasheet, PDF (102/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual
Signal Description
requires the bus, unless the LC302 core is disabled (then the BR, BG, and BGACK pins
should be used). After asserting the HALT signal, the external bus master must wait until
AS is negated plus 2 additional clocks before accessing the bus (to allow the LC302 to
threestate all of the bus signals).
BUSW—Bus Width Select
This input defines the M68000 processor mode (MC68000 or MC68008) and the data bus
width (16 bits or 8 bits, respectively). BUSW may only be changed upon a total system
reset. In 16-bit mode, all accesses to internal and external memory by the MC68000 core,
the IDMA, SDMA, and external master may be 16 bits, according to the assertion of the
UDS and LDS pins. In 8-bit mode, all M68000 core and IDMA accesses to internal and
external memory are limited to 8 bits. Also in 8-bit mode, SDMA accesses to external
memory are limited to 8 bits, but CP accesses to the CP side of the dual-port RAM con-
tinue to be 16 bits. In 8-bit mode, external accesses to internal memory are also limited to
8 bits at a time.
Low = 8-bit data bus, MC68008 core processor
High = 16-bit data bus, MC68000 core processor
DISCPU—Disable CPU (M68000 core)
The MC68LC302 can be configured to work solely with an external CPU. In this mode the
on-chip M68000 core CPU should be disabled by asserting the DISCPU pin high during
a total system reset (RESET and HALT asserted). DISCPU may only be changed upon a
total system reset.
The DISCPU pin, for instance, allows use of several LC302s to provide more than two
SCC channels without the need for bus isolation techniques. An external processor ser-
vices the other LC302s as peripherals (with their respective cores disabled).
FRZ
The FRZ pin is used to freeze the activity of selected peripherals. This is useful for system
debugging purposes. Refer to 3.1.4 Freeze Control for more details. FRZ should be con-
tinuously negated during total system reset.
5.5 ADDRESS BUS PINS (A19–A1)
The address bus pins are shown in Figure 5-4.
A19-A1
Figure 5-4. Address Bus Pins
MOTOROLA
MC68LC302 REFERENCE MANUAL
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