MC68LC302 Datasheet, PDF (151/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.21 AC ELECTRICAL SPECIFICATIONS—PCM TIMING
There are two sync types:
Short Frame—Sync signals are one clock cycle prior to the data
Long Frame—Sync signals are N-bits that envelope the data, N > 0; see Figure 6-21
and Figure 6-22).
Num.
300
301
301A
302
303
304
305
306
307
308
309
16.67 MHz 20 MHz
25 MHz
Characteristic
Min Max Min Max Min Max
L1CLK (PCM Clock) Frequency (see Note
1)
—
6.66
—
8.0
— 10.0
L1CLK Width Low
55 — 45 — 37 —
L1CLK Width High (see Note 4)
P+10 — P+10 — P+10 —
L1SY0–L1SY1 Setup Time to L1CLK
Rising Edge
0—0—0—
L1SY0–L1SY1 Hold Time from L1CLK
Falling Edge
40 — 33 — 27 —
L1SY0–L1SY1 Width Low
1—1—1—
Time Between Successive Sync Signals
(Short Frame)
8—8—8—
L1TxD Data Valid after L1CLK Rising Edge
(see Note 2)
0
70
0
60
0
47
L1TxD to High Impedance (from L1CLK
Rising Edge)
0 50 0 42 0 34
L1RxD Setup Time (to L1CLK Falling
Edge) (see Note 3)
20 — 17 — 14 —
L1RxD Hold Time (from L1CLK Falling
Edge) (see Note 3)
50 — 42 — 34 —
Unit
MHz
ns
ns
ns
ns
L1CLK
L1CLK
ns
ns
ns
ns
NOTES:
1. The ratio CLK/L1CLK must be greater than 2.5/1.
2. L1TxD becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are
used.
3. Specification valid for both sync methods.
4. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
6-34
MC68LC302 REFERENCE MANUAL
MOTOROLA