MC68LC302 Datasheet, PDF (147/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.19 AC ELECTRICAL SPECIFICATIONS—IDL TIMING (All timing measurements,
unless otherwise specified, are referenced to the L1CLK at 50% point of VDD) (see Figure 6-19)
16.67 MHz 20 MHz
25 MHz
Num.
Characteristic
Min Max Min Max Min Max ^Unit
260 L1CLK (IDL Clock) Frequency (see Note 1) — 6.66 — 8 — 10 MHz
261 L1CLK Width Low
55 — 45 — 37 — ns
262 L1CLK Width High (see Note 3)
P+10 — P+10 — P+10 — ns
263
L1TXD, L1RQ, SDS1–SDS2 Rising/Falling
Time
—
20
—
17
—
14
ns
264
L1SY1 (sync) Setup Time (to L1CLK Falling
Edge)
30
—
25
—
20
—
ns
265
L1SY1 (sync) Hold Time (from L1CLK Fall-
ing Edge)
50
—
40
—
34
—
ns
266 L1SY1 (sync) Inactive Before 4th L1CLK
0 — 0 — 0 — ns
267
L1TxD Active Delay (from L1CLK Rising
Edge)
0 75 0 65 0 50 ns
268
L1TxD to High Impedance (from L1CLK Ris-
ing Edge) (see Note 2)
0
50
0
42
0
34 ns
269 L1RxD Setup Time (to L1CLK Falling Edge) 50 — 42 — 34 — ns
270
L1RxD Hold Time (from L1CLK Falling
Edge)
50 — 42 — 34 — ns
271 Time Between Successive IDL syncs
20 — 20 — 20 — L1CLK
272 L1RQ Valid before Falling Edge of L1SY1 1 — 1 — 1 — L1CLK
273 L1GR Setup Time (to L1SY1 Falling Edge) 50 — 42 — 34 — ns
274 L1GR Hold Time (from L1SY1 Falling Edge) 50 — 42 — 34 — ns
275
SDS1–SDS2 Active Delay from L1CLK Ris-
ing Edge
10
75
10
65
7
50 ns
276
SDS1–SDS2 Inactive Delay from L1CLK
Falling Edge
10 75 10 65 7 50 ns
NOTES:
1. The ratio CLKO/L1CLK must be greater than 2.5/1.
2. High impedance is measured at the 30% and 70% of V_DD points, with the line at V_DD/2 through
10K in parallel with 130 pF.
3. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
6-30
MC68LC302 REFERENCE MANUAL
MOTOROLA