MC68LC302 Datasheet, PDF (50/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
3.4.2.2 Source Address Pointer Register (SAPR)
31
24 23
0
RESERVED
SOURCE ADDRESS POINTER
The SAPR is a 32-bit register.
Note that A23-A20 must be initialized by the user. They are driven internally by the IDMA
and can be used by the chip selects for address comparison.
3.4.2.3 Destination Address Pointer Register (DAPR)
The DAPR is a 32-bit register.
31
24 23
RESERVED
0
DESTINATION ADDRESS POINTER
Note that A23-A20 must be initialized by the user. They are driven internally by the IDMA
and can be used by the chip selects for address comparison.
3.4.2.4 Function Code Register (FCR)
The FCR is an 8-bit register.
7
6
4
3
2
0
1
DFC
1
SFC
The function codes must e initialized by the user. The function code value programmed into
the FCR is driven on the internal FC2-0 signals during a bus cycle to further qualify the ad-
dress bus value. These values may be used by the chip selects for address matching.
NOTE
This register is undefined following power-on reset. The user
should always initialize it and should not use the function code
value “111” in this register.
3.4.2.5 Byte Count Register (BCR)
This 16-bit register specifies the amount of data to be transferred by the IDMA; up to 64K
bytes (BCR = 0) is permitted.
3.4.2.6 Channel Status Register (CSR)
The CSR is an 8-bit register used to report events recognized by the IDMA controller. On
recognition of an event, the IDMA sets its corresponding bit in the CSR (regardless of the
INTE and INTN bits in the CMR).
7
4
3
2
1
0
RESERVED
DNS BES BED DONE
Bits 7–4—These bits are reserved for future use.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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