MC68LC302 Datasheet, PDF (88/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
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9
8
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0
NOF3 NOF2 NOF1 NOF0 C32 FSE — RTE FLG ENC
COMMON SCC MODE BITS
4.3.10.3 HDLC RECEIVE BUFFER DESCRIPTOR (RX BD) . The HDLC controller uses
the Rx BD to report information about the received data for each buffer. The Rx BD is shown
in Figure 4-4.
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9
8
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5
4
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2
1
0
OFFSET + 0 E
X
W
I
L
F
———
— LG NO AB CR OV CD
OFFSET + 2
DATA LENGTH
OFFSET + 4
OFFSET +6
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
Figure 4-4. HDLC Receive Buffer Descriptor
4.3.10.4 HDLC TRANSMIT BUFFER DESCRIPTOR (TX BD) . Data is presented to the
HDLC controller for transmission on an SCC channel by arranging it in buffers referenced
by the channel's Tx BD table. The Tx BD is shown in Figure 4-5.
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9
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2
1
0
OFFSET + 0 R
X
W
I
L TC — — — — — — — — UN CT
OFFSET + 2
DATA LENGTH
OFFSET + 4
TX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
OFFSET + 6
Figure 4-5. HDLC Transmit Buffer Descriptor
4.3.10.5 HDLC EVENT REGISTER . The SCC event register (SCCE) is called the HDLC
event register when the SCC is operating as an HDLC controller. It is an 8-bit register used
to report events recognized by the HDLC channel and to generate interrupts. Upon recog-
nition of an event, the HDLC controller sets its corresponding bit in the HDLC event register.
Interrupts generated by this register may be masked in the HDLC mask register. A bit is
cleared by writing a one; writing a zero does not affect a bit's value. All unmasked bits must
be cleared before the CP will clear the internal interrupt request. This register is cleared at
reset.
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6
CTS CD
5
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3
2
1
0
IDL TXE RXF BSY TXB RXB
4.3.10.6 HDLC MASK REGISTER. The SCC mask register (SCCM) is referred to as the
HDLC mask register when the SCC is operating as an HDLC controller. It is an 8-bit read-
write register that has the same bit formats as the HDLC event register. If a bit in the HDLC
mask register is a one, the corresponding interrupt in the event register will be enabled. If
the bit is zero, the corresponding interrupt in the event register will be masked. This register
is cleared upon reset.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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