MC68LC302 Datasheet, PDF (17/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
and HALT. The chip-select (CS) lines are not asserted on ac-
cesses to these locations. Thus, it is very helpful to use CS lines
to select external ROM/RAM that overlaps the BAR and SCR
register locations, since this prevents potential bus contention.
NOTE
In 8-bit system bus operation, IMP accesses are not possible un-
til the low byte of the BAR is written. Since the MOVE.W instruc-
tion writes the high byte followed by the low byte, this instruction
guarantees the entire word is written.
Do not assign other devices on the system bus an address that falls within the address
range of the peripherals defined by the BAR. If this happens, an internal BERR is generated
to the core (if the address decode conflict enable (ADCE) bit is set) and the address decode
conflict (ADC) bit in the SCR is set.
2.2.1 Base Address Register
The BAR is a 16-bit, memory-mapped, read-write register consisting of the high address
bits, the compare function code bit, and the function code bits. Upon a total system reset, its
value may be read as $BFFF, but its value is not valid until written by the user. The address
of this register is fixed at $0F2 in supervisor data space. BAR cannot be accessed in user
data space.
15
13
12
11
0
FC2–FC0
BASE ADDRESS
CFC
23
22
21
20
19
18
17
16
15
14
13 12
Bits 15–13—FC2–FC0
The FC2–FC0 field is contained in bits 15–13 of the BAR. These bits are used to set the
address space of 4K-byte block of on-chip peripherals. The address compare logic uses
these bits, dependent upon the CFC bit, to cause an address match within its address
space. When the core is enabled, the function code bits will be driven by the core to indi-
cate the type of cycle in process. In disable CPU mode, the FC pins are not present and
are internally driven to 5. Since, the user does not have any control over how the FC sig-
nals are driven, it is recommended that the user write these bits to zero and write the CFC
bit to zero to disable the FC comparison.
NOTE
Do not assign this field to the M68000 core interrupt acknowledge space (FC2–FC0 = 7).
CFC—Compare Function Code
0 = The FC bits in the BAR are ignored. Accesses to the IMP 4K-byte block occur with-
out comparing the FC bits.
1 = The FC bits in the BAR are compared. The address space compare logic uses the
FC bits to detect address matches.
2-4
MC68LC302 REFERENCE MANUAL
MOTOROLA