MC68LC302 Datasheet, PDF (75/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
Table 4-2. UART Specific Parameter RAM
Address
SCC Base + 9C #
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2 #
SCC Base + A4 #
SCC Base + A6 #
SCC Base + A8 #
SCC Base + AA #
SCC Base + AC #
SCC Base + AE
SCC Base + B0 #
SCC Base + B2 #
SCC Base + B4 #
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
Name
MAX_IDL
IDLC
BRKCR
PAREC
FRMEC
NOSEC
BRKEC
UADDR1
UADDR2
RCCR
CHARACTER1
CHARACTER2
CHARACTER3
CHARACTER4
CHARACTER5
CHARACTER6
CHARACTER7
CHARACTER8
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Description
Maximum IDLE Characters (Receive)
Temporary Receive IDLE Counter
Break Count Register (Transmit)
Receive Parity Error Counter
Receive Framing Error Counter
Receive Noise Counter
Receive Break Condition Counter
UART ADDRESS Character 1
UART ADDRESS Character 2
Receive Control Character Register
CONTROL Character 1
CONTROL Character 2
CONTROL Character 3
CONTROL Character 4
CONTROL Character 5
CONTROL Character 6
CONTROL Character 7
CONTROL Character 8
# Initialized by the user (M68000 core).
4.3.8.2 UART MODE REGISTER. Each SCC mode register is a 16-bit, memory- mapped,
read-write register that controls the SCC operation. The read-write UART mode register is
cleared by reset.
15
14
13
12
11
10
9
8
7
6
5
0
TPM1 TPM0 RPM PEN UM1 UM0 FRZ CL RTSM SL
COMMON SCC MODE BITS
4.3.8.3 UART RECEIVE BUFFER DESCRIPTOR (RX BD). The CP reports information
about each buffer of received data by its BDs. The Rx BD is shown in Figure 4-2.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OFFSET + 0 E
X
W
I
C
A
M
ID —
— BR FR PR — OV CD
OFFSET + 2
DATA LENGTH
OFFSET + 4
OFFSET +6
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
Figure 4-2. UART Receive Buffer Descriptor
4.3.8.4 UART TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is presented to the CP
for transmission on an SCC channel by arranging it in buffers referenced by the channel's
Tx BD table. The Tx BD shown in Figure 4-3.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OFFSET + 0 R
X
W
I CR A
P — — — — — — — — CT
OFFSET + 2
DATA LENGTH
OFFSET + 4
OFFSET +6
TX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
Figure 4-3. UART Transmit Buffer Descriptor
4-8
MC68LC302 REFERENCE MANUAL
MOTOROLA