MC68LC302 Datasheet, PDF (65/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
3.8.2 Disable CPU Logic (M68000)
The IMP can be configured to operate solely as a peripheral to an external processor. In this
mode, the on-chip M68000 CPU should be disabled by strapping DISCPU high during sys-
tem reset (RESET and HALT asserted simultaneously). The internal accesses to the IMP
peripherals and memory may be asynchronous or synchronous. During synchronous reads,
one wait state may be used if required (EMWS bit set). The following pins change their func-
tionality in this mode:
1. THE IPL0 pin becomes BR and is an output from the IDMA and SDMA to the external
M68000 bus.
2. The IPL2 pin becomes BG and is an input to the IDMA and SDMA from the external
M68000 bus. When BG is sampled as low by the IMP, it waits for AS, HALT, and
BGACK to be negated, and then asserts BGACK and performs one or more bus cy-
cles.
3. The IPL1 pin becomes BGACK and is an output from the IDMA and SDMA to indicate
bus ownership.
4. The IPL2-0 lines are no longer encoded interrupt lines.The interrupt controller will out-
put the MC68LC302’s interrupt request on IOUT2. CS0, which is multiplexed with
IOUT2 is not available in this mode.
5. The WEH and WEL signals become UDS and LDS respectively.
6. The OE becomes R/W.
DISCPU should remain continuously high during disable CPU mode operation. Although the
CS0 pin is not available as an output from the device in disable CPU mode, it may be en-
abled to provide DTACK generation. In disable CPU mode, BR0 is initially $C000.
In disable CPU mode, accesses by an external master to the IMP RAM and registers may
be asynchronous or synchronous to the IMP clock. See the SAM and EMWS bits in the SCR
for details.
3.8.3 Bus Arbitration Logic
Both internal and external bus arbitration are discussed in the following paragraphs.
3.8.3.1 Internal Bus Arbitration
The IMP bus arbiter supports three bus request sources in the following standard priority:
1. External bus master (BR pin) (only in Disable CPU mode)
2. SDMA for the SCCs (six channels)
3. IDMA (one channel)
3.8.3.2 External Bus Arbitration
When the CPU is enabled, an external bus master may gain ownership of the M68000 bus
by asserting the HALT signal. This will cause the LC302 bus master (M68000 core, SDMA,
or IDMA) to stop at the completion of the current bus cycle After asserting the HALT signal,
the external bus master must wait until AS is negated plus 2 additional system clocks before
accessing the bus (to allow the LC302 to threestate all of the bus signals).After gaining own-
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MC68LC302 REFERENCE MANUAL
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