MC68LC302 Datasheet, PDF (163/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Index
Bus Arbitration Pins 5-10
Bus Control Pins 5-9
Bus States during Low power modes
68000 2-15
BUSW 2-1, 5-7
C
Changes to IMP
CLKO Drive Options 2-6
Three-state TCLK1 2-6
Three-state RCLK1 2-6
Chip-Select 2-4
AS 3-25
Base Address 3-27
Base Register 3-26
CS0 3-26, 3-28, 5-21
DTACK 3-26
Option Register 3-26
Chip-Select Pins 5-21
Chip-Select Registers 3-26
Chip-Select Timing 6-24
CLKO
Output Buffer Strength 2-11
CLKOMOD1–2 2-6
Clock
CLKO 5-4
Clock Pins 5-4
CMOS Level 5-2
CMR 3-11
Communications Processor 4-1
Configuration
MC68302 IMP Control 2-3
CQFP 7-2
Crystal Oscillator 2-8
Crystal Oscillator Circuit (IMP) 2-9
CS0 3-26, 3-28, 5-21
CS1 2-23, 2-24, 5-21
CS2 2-23, 2-24
CS3 2-23, 3-26, 5-1, 5-10, 5-21
CS3–CS1 5-21
CSelect 2-7
CSR 3-13
D
DAPR 3-13
Data Bus Pins 5-8
Default System Clock Generation 2-7
DF0–3 2-10
Disable CPU 5-7
BG 3-28
BR 3-28
CS0 3-28
DTACK 3-28
EMWS 3-28
SAM 3-28
Disable CPU Logic 3-28
Disable SCC1 Serial Clocks Out 4-4
DISC 4-4
DISCPU 3-28, 5-7
Divide by Two Block
From Tin1 pin 4-5
DMA Control 3-10
DOZE 2-13, 2-16
DRAM Refresh
Buffer Descriptors 3-29
PB8 3-18
Drive 2-13
DSR 4-6
DTACK 3-4, 3-26, 3-28, 5-10, 5-12
Dynamic RAM Refresh Controller 3-29
E
EMWS (External Master Wait State) 3-4, 3-5,
3-28
Enable Receiver 4-5
Enable Transmitter 4-6
Exception
PB8 3-29
EXTAL 5-2, 5-4
External
Bus Master 3-28
External Bus Arbitration using HALT 3-28
Master Wait State (EMWS) 3-5
External Bus Arbitration 3-28
External Master Wait State 3-4
F
FCR 3-13
Freeze Control 3-5
FRZ 5-7
Function Codes 3-13, 5-12
Comparison 2-4
FC2-FC0 2-4, 5-12
Register 3-13
INDEX-2
MC68LC302 REFERENCE MANUAL
MOTOROLA