MC68LC302 Datasheet, PDF (49/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
NOTE
The settings 10 and 11 will not work since the DREQ pin is not
present.
SAPI—Source Address Pointer (SAP) Increment
0 = SAP is not incremented after each transfer.
1 = SAP is incremented by one or two after each transfer, according to the source size
(SSIZE) bits and the starting address.
DAPI—Destination Address Pointer (DAP) Increment
0 = DAP is not incremented after each transfer.
1 = DAP is incremented by one or two after each transfer, according to the destination
size (DSIZE) bits and the starting address.
SSIZE—Source Size
00 = Reserved
01 = Byte
10 = Word
11 = Reserved
DSIZE—Destination Size
00 = Reserved
01 = Byte
10 = Word
11 = Reserved
BT—Burst Transfer
00 = IDMA gets up to 75% of the bus bandwidth.
01 = IDMA gets up to 50% of the bus bandwidth.
10 = IDMA gets up to 25% of the bus bandwidth.
11 = IDMA gets up to 12.5% of the bus bandwidth.
RST—Software Reset
0 = Normal operation
1 = The channel aborts any external pending or running bus cycles and terminates
channel operation. Setting RST clears all bits in the CSR and CMR.
STR—Start Operation
0 = Stop channel; clearing this bit will cause the IDMA to stop transferring data at
the end of the current operand transfer. The IDMA internal state is not altered.
1 = Start channel; setting this bit will allow the IDMA to start (or continue if previously
stopped) transferring data.
NOTE
STR is cleared automatically when the transfer is complete.
3-12
MC68LC302 REFERENCE MANUAL
MOTOROLA