MC68LC302 Datasheet, PDF (108/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
Table 5-3. Bus Signal Summary—Core and External Master
Signal Name²
Pin Type
M68000 Core Master
Access To
Internal
Memory
Space
External
Memory
Space
External Master
Access To¹
Internal
Memory
Space
External
Memory
Space
A19–A1,AS, UDS, LDS, RW
I/O
O
O
I
I
WEH,WEL,OE
I/O
O
O
O*
O*
D15–D0 Read
I/O
O
I
O
I
D15–D0 Write
I/O
O
O
I
I
DTACK
I/O
O
**
O
**
(BR)
I/O Open Drain
NA
NA
N/A
N/A
(BG)
I
NA
NA
N/A
N/A
(BGACK)
I/O
NA
NA
I
I
HALT
I/O Open Drain
I/O
I/O
I
I
RESET
I/O Open Drain
I/O
I/O
I
I
IPL2–IPL0
I
I
I
NA
NA
AVEC
I
I
I
I
I
IOUT2
O
O
O
O
O
1_{External Masters are only directly supported in Disable CPU mode.}
2_{Signal Names in parentheses are only available in Disable CPU mode.}
* WEH,WEL,OE are threestate when External Master Acquires the Bus with HALT
**If DTACK is generated automatically (internally) by the chip-select logic, then it is an output. Otherwise, it is an
input.
Table 5-4. Bus Signal Summary—IDMA and SDMA
Signal Name¹
Pin Type
IDMA Master
Access To
Internal
Memory
Space
External
Memory
Space
SDMA Master
Access To
Internal
Memory
Space
External
Memory
Space
A19–A1,AS, UDS, LDS, RW
I/O
O
O
N/A
O
WEH,WEL,OE
I/O
O
O
N/A
O
D15—D0 Read
I/O
O
I
N/A
I
D15—D0 Write
I/O
O
O
N/A
O
DTACK
I/O
O
**
N/A
**
(BR)
I/O
O ##
O ##
N/A
O ##
(BG)
I/O
I ##
I ##
N/A
I ##
(BGACK)
I/O
O##
O##
N/A
O##
HALT
I/O Open Drain
I
I
N/A
I
RESET
I/O Open Drain
I
I
N/A
I
1 _{Signal Names in parentheses are only available in Disable CPU mode.}
**If DTACK is generated automatically (internally) by the chip-select logic, then it is an output. Otherwise, it is
an input.#Applies to disable CPU mode only. The internal signal IBCLR is used otherwise.
##_{Applies to disable CPU mode only, otherwise N/A.}
MOTOROLA
MC68LC302 REFERENCE MANUAL
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