MC68LC302 Datasheet, PDF (62/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
PTEN—Periodic Timer Enable
This bit contains the enable control for the periodic timer.
0 = Periodic timer is disabled
1 = Periodic timer is enabled
PTP—Periodic Timer Prescaler Control
This bit contains the prescaler control for the periodic timer.
0 = Periodic timer clock is not prescaled
1 = Periodic timer clock is prescaled by a value of 512
PITR10–0—Periodic Interrupt Timer Register Bits
These bits of the PITR contain the remaining bits of the PITR count value for the periodic
timer. These bits may be written only when the PIT is disabled (PTEN=0) to modify
the PIT count value.
NOTE
If the PIT is enabled with the PTP bit is set, the first interrupt can
be up to 512 clocks early, depending on the prescaler counter
value when the PIT is enabled.
3.8 EXTERNAL CHIP-SELECT SIGNALS AND WAIT-STATE LOGIC
The IMP provides a set of four programmable chip-select signals. Each chip-select signal
has an identical internal structure. For each memory area, the user may also define an in-
ternally generated cycle termination signal (DTACK). This feature eliminates board space
that would be necessary for cycle termination logic.
The chip-select logic is active for memory cycles generated by internal bus masters
(M68000 core, IDMA, SDMA, DRAM refresh) or external bus masters (A23-A20 are driven
to zero internally and FC2-0 are driven to 5). These signals are driven externally on the
falling edge of AS and are valid shortly after AS goes low.
NOTE
For more information on the operation of the Chip Selects,
please refer to Section 3 of the MC68302 Users’ Manual.
NOTE
Internal Masters (CPU, IDMA and SDMA) drive A23:A20 and
FC2-FC0 internally. The CS logic compares the signals to the
values programmed in the registers.
In Disable CPU mode or for External Bus Masters, the A23-A20
signals are internally driven to zero, so the user must program
MOTOROLA
MC68LC302 REFERENCE MANUAL
3-25