MC68LC302 Datasheet, PDF (45/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
executing from the first location of the dual-port RAM to complete the boot process. This
function is not supported for SCC2.
Three pins are sampled to determine the mode of operation and clock of the boot function:
PA7–Sampled during Hard Reset (RESET and HALT asserted)
0 Boot from SCC is enabled
1 Boot from SCC is disabled
PA5–Sampled within 100 clocks from the negation of RESET
0 Internal Clock
1 External Clock 16* the bit rate on TCLK1 and RCLK1
PA12 (MODCLK0) Sampled during Hard Reset (RESET and HALT asserted)
0 Nominal input frequency on EXTAL is 4.192 Mhz
1 Nominal input frequency on EXTAL is 32.768 Khz
To enable the boot function, the PA7 pin must be pulled low during system reset. (System
reset is defined by the RESET and HALT pins being asserted.) The PA7 pin must be pulled
high during system reset, if boot mode is not to be enabled. Once the MC68LC302 detects
that the PA7 pin is asserted, it internally keeps the HALT signal to the 68K core asserted
after system reset is complete. This action prevents the 68000 from fetching the reset vec-
tor.
NOTE
PA7 needs to be either pulled UP or pulled DOWN. Do not leave
this pin floating during reset.
Once system reset is complete, the RISC processor programs the BAR register to $0000 to
place the dual-port RAM at the low end of system memory. It then samples the PA5 pin to
determine the clock source for the UART.
NOTE
PA5 is expected to be valid for 100 clocks after the negation of
RESET.
If PA5 is pulled high, SCC1 is programmed for external clocks. In this mode, the user has to
connect an external clock 16* the bit rate to TCLK1 and RCLK1.
If PA5 is pulled low, the SCC is programmed for internal clocks and the TCLK1 and RCLK1
pins are programmed to three-state to avoid contention with user clocks. The RISC proces-
sor then programs the SCON register of the SCC based on PA12. The PA12 value sampled
during reset (MODCLK0) is decoded in order to provide ~9600 bps with two input frequen-
cies (4.192 Mhz and 32.768 Khz).
• If MODCLK0 = GND, SCON1 is programmed to 0x00D8.
3-8
MC68LC302 REFERENCE MANUAL
MOTOROLA