MC68LC302 Datasheet, PDF (103/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
A19—A1 form a 20-bit address bus when combined with WEH/UDS. The address bus is a
bidirectional, three-state bus capable of addressing 1M bytes of data (including the LC302
internal address space). It provides the address for bus operation during all cycles except
CPU space cycles. In CPU space cycles, the CPU reads a peripheral device vector number.
These lines are outputs when the LC302 (M68000 core, SDMA or IDMA) is the bus master
and are inputs otherwise (in DISCPU only).
NOTE:
Since internally the CS logic compares also A23-A20 the effec-
tive address space for internal masters is 4 M bytes.
5.6 DATA BUS PINS (D15—D0)
The data bus pins are shown in Figure 5-5. When the MC68LC302 is in 8-bit data bus mode,
D15-D8 become general purpose I/O pins, PN15-PN8.
D0-D7
D15-D8/PN15-8
Figure 5-5. Data Bus Pins
This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transmit
and accept data in either word or byte lengths. For all 16-bit LC302 accesses, byte 0, the
high-order byte of a word, is available on D15–D8, conforming to the standard M68000 for-
mat.
When working with an 8-bit bus (BUSW is low), the data is transferred through the low-order
byte (D7–D0). The high-order byte (D15–D8) is not used for data transfer, and those pins
can be used as 8 general purpose I/O ports (PNIO).
5-8
MC68LC302 REFERENCE MANUAL
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