MC68LC302 Datasheet, PDF (52/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
IV7—Level 7 Interrupt Vector (Internal Vector Generation Should Be Used)
0 = Internal vector.
1 = External vector.
IV6—Level 6 Interrupt Vector (Internal Vector Generation Should Be Used)
0 = Internal vector.
1 = External vector.
IV1—Level 1 Interrupt Vector (Internal Vector Generation Should Be Used)
0 = Internal vector.
1 = External vector.
ET7—IRQ7 Edge-/Level-Triggered
0 = Level-triggered. An interrupt is made pending when IRQ7 is low.
NOTE
The M68000 always treats level 7 as an edge-sensitive interrupt.
1 = Edge-triggered. An interrupt is made pending when IRQ7 changes from one to
zero (falling edge).
ET6—IRQ6 Edge-/Level-Triggered
0 = Level-triggered. An interrupt is made pending when IRQ6 is low.
1 = Edge-triggered. An interrupt is made pending when IRQ6 changes from one to
zero (falling edge).
ET1—IRQ1 Edge-/Level-Triggered
0 = Level-triggered. An interrupt is made pending when IRQ1 is low.
1 = Edge-triggered. An interrupt is made pending when IRQ1 changes from one to
zero (falling edge).
V7–V5—Interrupt Vector Bits 7–5
These three bits are concatenated with five bits provided by the interrupt controller, which
indicate the specific interrupt source, to form an 8-bit interrupt vector number. If these bits
are not written, the vector $0F is provided.
NOTE:
These three bits should be greater than or equal to ‘010’ in order
to put the interrupt vector in the area of the exception vector ta-
ble for user vectors.
Bits 11 and 4–0—Reserved for future use.
3.5.2.2 Interrupt Pending Register (IPR)
Each bit in the 16-bit IPR corresponds to an INRQ interrupt source. When an INRQ interrupt
is received, the interrupt controller sets the corresponding bit in the IPR.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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