MC68LC302 Datasheet, PDF (48/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
The rest of the functionality remains the same as for the MC68302. For details on the bus
operation, please refer to the MC68302 User’s Manual.
3.4.2 IDMA Registers (Independent DMA Controller)
The IDMA has six registers that define its specific operation. These registers include a 32-
bit source address pointer register (SAPR), a 32-bit destination address pointer register
(DAPR), an 8-bit function code register (FCR), a 16-bit byte count register (BCR), a 16-bit
channel mode register (CMR), and an 8-bit channel status register (CSR).
3.4.2.1 Channel Mode Register (CMR)
The CMR, a 16-bit register, is reset to $0000.
15
14
13
12
11
10
9
8
7
6
— ECO INTN INTE
REQG
SAPI DAPI
SSIZE
5
4
DSIZE
3
2
1
0
BT
RST STR
Bit 15—Reserved for future use.
ECO—External Control Option (NOT USED)
0 = If the request generation is programmed to be external in the REQG bits, the con-
trol signals (DACK and DONE) are used in the source (read) portion of the transfer
since the peripheral is the source.
1 = If the request generation is programmed to be external in the REQG bits, the con-
trol signals (DACK and DONE) are used in the destination (write) portion of the
transfer since the peripheral is the destination.
INTN—Interrupt Normal
0 = When the channel has completed an operand transfer without error conditions, the
channel does not generate an interrupt request to the IMP interrupt controller. The
DONE bit remains set in the CSR.
1 = When the channel has completed an operand transfer without error conditions, the
channel generates an interrupt request to the IMP interrupt controller and sets
DONE in the CSR.
INTE—Interrupt Error (Only the internal BERR signal will be used.)
0 = If a bus error occurs during an operand transfer either on the source read (BES) or
the destination write (BED), the channel does not generate an interrupt to the IMP
interrupt controller. The appropriate bit remains set in the CSR.
1 = If a bus error occurs during an operand transfer either on BES or BED, the channel
generates an interrupt to the IMP interrupt controller and sets the appropriate bit
(BES or BED) in the CSR.
REQG—Request Generation (External request is not supported)
00 = Internal request at limited rate (limited burst bandwidth) set by burst transfer (BT)
bits
01 = Internal request at maximum rate (one burst)
10 = External request burst transfer mode (DREQ level sensitive)
11 = External request cycle steal (DREQ edge sensitive)
MOTOROLA
MC68LC302 REFERENCE MANUAL
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