MC68LC302 Datasheet, PDF (89/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
4.3.11 BISYNC Controller
The functionality of the BISYNC controller has not changed. For any additional information
on parameters, registers, and functionality, please refer to the MC68302 Users’ Manual.
4.3.11.1 BISYNC MEMORY MAP. When configured to operate in BISYNC mode, the IMP
overlays the structure listed in Table 4-10 onto the protocol-specific area of that SCC param-
eter RAM. Refer to System Configuration Registers on page 5 for the placement of the three
SCC parameter RAM areas and Table 4-1 for the other parameter RAM values.
Table 4-10. BISYNC Specific Parameter RAM
Address
SCC Base + 9C
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2
SCC Base + A4 #
SCC Base + A6
SCC Base + A8
SCC Base + AA #
SCC Base + AC #
SCC Base + AE #
SCC Base + B0 #
SCC Base + B2 #
SCC Base + B4 #
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
Name
RCRC
CRCC
PRCRC
TCRC
PTCRC
RES
RES
PAREC
BSYNC
BDLE
CHARACTER1
CHARACTER2
CHARACTER3
CHARACTER4
CHARACTER5
CHARACTER6
CHARACTER7
CHARACTER8
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Description
Temp Receive CRC
CRC Constant
Preset Receiver CRC 16/LRC
Temp Transmit CRC
Preset Transmitter CRC 16/LRC
Reserved
Reserved
Receive Parity Error Counter
BISYNC SYNC Character
BISYNC DLE Character
CONTROL Character 1
CONTROL Character 2
CONTROL Character 3
CONTROL Character 4
CONTROL Character 5
CONTROL Character 6
CONTROL Character 7
CONTROL Character 8
# Initialized by the user (M68000 core).
4.3.11.2 BISYNC MODE REGISTER. Each SCC mode register is a 16-bit, memory-
mapped, read-write register that controls the SCC operation. The term BISYNC mode reg-
ister refers to the protocol-specific bits (15–6) of the SCC mode register when that SCC is
configured for BISYNC. The read-write BISYNC mode register is cleared by reset.
15
14
13
12
11
10
9
8
7
6
5
0
PM EXSYN NTSYN REVD BCS
—
RTR RBCS SYNF ENC COMMON SCC MODE BITS
4.3.11.3 BISYNC RECEIVE BUFFER DESCRIPTOR (RX BD). The CP reports information
about the received data for each buffer using BD. The Rx BD is shown in Figure 4-6
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OFFSET + 0 E
X
W
I
C
B — — — — — DL PR CR OV CD
OFFSET +2
DATA LENGTH
OFFSET +4
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
OFFSET + 6
Figure 4-6. BISYNC Receive Buffer Descriptor
4.3.11.4 BISYNC TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is presented to the
CP for transmission on an SCC channel by arranging it in buffers referenced by the chan-
nel's Tx BD table. The Tx BD is shown in Figure 4-7.
4-22
MC68LC302 REFERENCE MANUAL
MOTOROLA