MC68LC302 Datasheet, PDF (91/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
Table 4-11. Transparent-Specific Parameter RAM
Address
SCC BASE + 9C
SCC BASE + 9E
SCC BASE + A0
SCC BASE + A2
SCC BASE + A4
SCC BASE + A6
SCC BASE + A8
SCC BASE + AA
SCC BASE + AC
SCC BASE + AE
SCC BASE + B0
SCC BASE + B2
SCC BASE + B4
SCC BASE + B6
SCC BASE + B8
SCC BASE + BA
SCC BASE + BC
SCC BASE + BE
Name
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Width
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4.3.12.2 TRANSPARENT MODE REGISTER. Each SCC mode register is a 16-bit, mem-
ory-mapped, read-write register that controls the SCC operation. The term transparent
mode register refers to the protocol-specific bits (15–6) of the SCC mode register when that
SCC is configured for transparent mode. The transparent mode register is cleared by reset.
All undefined bits should be written with zero.
15
14
13
12
11
10
9
8
7
6
5
0
— EXSYN NTSYN REVD —
—
—
—
—
—
COMMON SCC MODE BITS
4.3.12.3 TRANSPARENT RECEIVE BUFFER DESCRIPTOR (RXBD) . The CP reports
information about the received data for each buffer using BD. The RxBD is shown in Figure
4-8.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OFFSET + 0 E
X
W
I
—
————
———
— — OV CD
OFFSET + 2
DATA LENGTH
OFFSET + 4
OFFSET +6
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
Figure 4-8. Transparent Receive Buffer Descriptor
4-24
MC68LC302 REFERENCE MANUAL
MOTOROLA