MC68LC302 Datasheet, PDF (71/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
4.2.1.2 SERIAL INTERFACE MASK REGISTER (SIMASK) . The SIMASK register, a
memory-mapped read-write register, is set to all ones by reset. SIMASK is used in IDL and
GCI to determine which bits are active in the B1 and B2 channels. Any combination of bits
may be chosen. A bit set to zero is not used by the IMP. A bit set to one signifies that the
corresponding B channel bit is used for transmission and reception on the B channel. Note
that the serial data strobes, SD1 and SD2, are asserted for the entire 8-bit time slot inde-
pendent of the setting of the bits in the SIMASK register.
15
8
7
0
B2
NOTE
Bit 0 of this register is the first bit transmitted or received on the
IDL/GCI B1 channel.
4.3 SERIAL COMMUNICATION CONTROLLERS (SCCS)
The IMP contains two independent SCCs, each of which can implement different protocols.
This configuration provides the user with options for controlling up to two independent full-
duplex lines implementing bridges or gateway functions or multiplexing both SCCs onto the
same physical layer interface to implement a two channels on a time-division multiplexed
(TDM) bus. Each protocol-type implementation uses identical buffer structures to simplify
programming.
4.3.1 SCC Configuration Register (SCON)
Each SCC controller has a configuration register that controls its operation and selects its
clock source and baud rate. This register has not been changed from the MC68302.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WOMS EXTC TCS RCS CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 DIV4
4.3.1.1 DIVIDE BY 2 INPUT BLOCKS (NEW FEATURE). The SCC Baud Rate Generators
have 2 divide by 2 blocks added to them. With the divide by 2 blocks enabled, the VCO Out-
put from the PLL and the TIN1 input clock can be divided by 2 before they are used by the
BRG to generate the serial clocks. The divide by two blocks can be enabled by setting the
BCD bit in the IOMCR register if the BRG clock source is derived from the IMP system clock,
or by setting the BRGDIV bit in the DISC register if the BRG clock source is derived from the
TIN pin.
4.3.2 Disable SCC1 Serial Clocks Out (DISC)
The Disable SCC1 Serial Clocks Out (DISC) is an 16-bit read/write register. The upper 8 bits
control: (1) enabling the divide by 2 prescaler for the baud rate generator from the TIN1 pin,
and (2) options for three stating theTCLK1, and RCLK1 pins.
4-4
MC68LC302 REFERENCE MANUAL
MOTOROLA