MC68LC302 Datasheet, PDF (55/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
Table 3-2. Port A Pin Functions
3.6.3 Port B
PACNT Bit = 1
Pin Function
PACNT Bit = 0
Pin Function
Input to
SCC2/SCC3/IDMA
RXD2
PA0
TXD2
PA1
GND
—
RCLK2
PA2
TCLK2
PA3
CTS2
PA4
GND
RCLK2 #
GND
RTS2
PA5
CD2
PA6
SDS2/BRG2
PA7
—
GND
—
SPRXD
SPTXD
SPCLK
PA8
PA9
PA10
GND
—
GND
NA
PA12
—
# Allows a single external clock source on the RCLK pin to clock both
the SCC receiver and transmitter.
Port B has 12 pins; however only eight are connected externally.
3.6.3.1 PB7–PB3
Each port B pin may be configured as a general-purpose I/O pin or as a dedicated peripheral
interface pin. PB7–PB3 is controlled by the port B control register (PBCNT), the port B data
direction register (PBDDR), and the port B data register (PBDAT), and PB7 is configured as
an open-drain output (WDOG) upon total system reset.
Table 3-3 shows the dedicated function of each pin. The third column shows the input to the
peripheral when the pin is used as a general-purpose I/O pin.
Table 3-3. Port B Pin Functions
PBCNT Bit = 1
Pin Function
TIN1
TIN2
TOUT2
WDOG
PBCNT Bit = 0
Pin Function
PB3
PB5
PB6
PB7
Input to Interrupt
Control and Timers
GND
GND
—
—
3.6.3.2 PB11–PB8
PB11–PB8 are four general-purpose I/O pins continuously available as general-purpose I/
O pins and, therefore, are not referenced in the PBCNT. PB8 operates like PB11–PB9 ex-
cept that it can also be used as the DRAM refresh controller request pin, as selected in the
system control register (SCR).
3-18
MC68LC302 REFERENCE MANUAL
MOTOROLA