MC68LC302 Datasheet, PDF (15/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
The MC68LC302 in CPU enable mode has an output enable (OE) signal instead of R/W.
The OE signal indicates that the MC68LC302 expects an external device to drive data onto
the data bus. When the core is disabled, OE becomes the R/W signal.
The MC68LC302 in CPU enable mode does not have BR, BG, and BGACK pins. Instead
the HALT pin is used to force the MC68LC302 off of the bus (see the HALT signal descrip-
tion in 5.4 System Control Pins). While the MC68LC302 is halted, the chip selects are still
functional. The external master will not be able to access the internal registers and dual-port
RAM.
When the core is disabled, the IPL0, IPL1, and IPL2 lines become the BR, BG, and BGACK
signals. The only external interrupts handled are PB8, PB9, PB10, and PB11.
Two M6800 signals are omitted from the 68LC302: valid memory address (VMA) and enable
(E). The valid peripheral address (VPA) signal which was used on the MC68302 as AVEC
has been removed from the MC68LC302.
The signals for the serial communications port (SCP) have been multiplexed with the PA8,
PA9, and PA10 pins and the signals for SCC3 have been removed.
The FC2-0 pins have been removed from the MC68LC302. These signals are still driven
internally by the core depending on the type of bus cycle (i.e. supervisor program space,
supervisor data space, etc.) and the internal peripherals. They can still be used for address
comparison in the chip select registers. In disable CPU mode and when HALT is asserted
for external masters, the FC signals are internally driven to 5 for external master accesses
to internal peripherals.
The A23-A20 pins have been removed from the MC68LC302. These signals are still driven
internally by the core and the internal peripherals. The user must program the full 24-bit
address in the chip select base registers, option registers, and in the pointers used by the
internal DMA and SCCs. In disable CPU mode and when HALT is asserted for external mas-
ters, the A23-20 signals are driven to zero for all external master accesses.
The other signals removed from the MC68LC302 are IAC, RMC, BLCR, BERR, FRZ, BRG1,
DREQ/PA13, DACK/PA14, DONE/PA15, IACK7/PB0, IACK6/PB1, IACK7/PB2, and
TOUT1/PB4.
The signals XFC and MODCLK (multiplexed with PA12) have been added for use with the
on-chip phase lock loop.
For purposes of emulation support only, a special 132 PGA version is supported. This ver-
sion adds back the FC2-0, IAC, FRZ, and AVEC pins.
2.2 IMP CONFIGURATION CONTROL
A number of reserved entries in the external M68000 exception vector table are used as
addresses for the internal system configuration registers. See Table 2-1.
2-2
MC68LC302 REFERENCE MANUAL
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