MC68LC302 Datasheet, PDF (87/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
PM (parity mode)
0 = Even parity
1 = Odd parity
The autobaud controller issues a Tx interrupt after each character is transmitted.
4.3.9.9 REPROGRAMMING TO UART MODE OR ANOTHER PROTOCOL. The following
steps should be followed in order to switch the SCC from autobaud to UART mode or to
another protocol.
• Disable the SCC by clearing ENR and ENT.
• Issue the Enter_Hunt_Mode command.
• Initialize the SCC parameter RAM (specifically, the Rx and Tx internal states and the
words containing the Rx and Tx BD#s) to the state immediately after reset and initialize
the protocol specific parameter area for the new protocol.
• Re-enable the SCC with the new mode.
4.3.10 HDLC Controller
The functionality of the HDLC controller has not changed. For any additional information on
parameters, registers, and functionality, please refer to the MC68302 Users’ Manual.
4.3.10.1 HDLC MEMORY MAP . When configured to operate in HDLC mode, the IMP over-
lays the structure shown in Table 4-8 onto the protocol-specific area of that SCC parameter
RAM. Refer to Parameter RAM on page 21 for the placement of the three SCC parameter
RAM areas and to Table 4-1 for the other parameter RAM values.
Table 4-9. HDLC-Specific Parameter RAM
Address
SCC Base + 9C
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2 #
SCC Base + A4
SCC Base + A6
SCC Base + A8 #
SCC Base + AA #
SCC Base + AC #
SCC Base + AE #
SCC Base + B0 #
SCC Base + B2 #
SCC Base + B4
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
Name
RCRC_L
RCRC_H
C_MASK_L
C_MASK_H
TCRC_L
TCRC_H
DISFC
CRCEC
ABTSC
NMARC
RETRC
MFLR
MAX_cnt
HMASK
HADDR1
HADDR2
HADDR3
HADDR4
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Description
Temp Receive CRC Low
Temp Receive CRC High
Constant ($F0B8 16-Bit CRC, $DEBB 32-Bit CRC)
Constant ($XXXX 16-Bit CRC, $20E3 32-Bit CRC)
Temp Transmit CRC Low
Temp Transmit CRC High
Discard Frame Counter
CRC Error Counter
Abort Sequence Counter
Nonmatching Address Received Counter
Frame Retransmission Counter
Max Frame Length Register
Max_Length Counter
User-Defined Frame Address Mask
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
# Should be initialized by the user (M68000 core).
4.3.10.2 HDLC MODE REGISTER . Each SCC mode register is a 16-bit, memory-mapped,
read-write register that controls the SCC operation. The read-write HDLC mode register is
cleared by reset.
4-20
MC68LC302 REFERENCE MANUAL
MOTOROLA