MC68LC302 Datasheet, PDF (107/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
signals an interrupt acknowledge through A19–A16 to ensure that the interrupt is properly
recognized.
As IRQ1, IRQ6, and IRQ7 (dedicated mode), these inputs indicate to the MC68LC302 that
an external device is requesting an interrupt. Level 7 is the highest level and cannot be
masked. Level 1 is the lowest level. Each one of these inputs (except for level 7) can be
programmed to be either level-sensitive or edge-sensitive. The M68000 always treats a
level 7 interrupt as edge sensitive.
FC2–FC0—Function Codes 2–0
These bidirectional signals indicate the state and the cycle type currently being executed.
The information indicated by the function code outputs is valid whenever AS is active.
These lines are outputs when the IMP (M68000 core, SDMA, or IDMA) is the bus master
and are inputs otherwise. The function codes output by the M68000 core are predefined;
whereas, those output by the SDMA and IDMA are programmable. The function code
lines are inputs to the chip-select logic and IMP internal register decoding in the BAR.
AVEC—Autovector Input/Interrupt Output
In normal operation, this signal functions as the input AVEC. AVEC, when asserted during
an interrupt acknowledge cycle, indicates that the M68000 core should use automatic
vectoring for an interrupt. This pin operates like VPA on the MC68000, but is used for au-
tomatic vectoring only. AVEC instead of DTACK should be asserted during autovectoring
and should be high otherwise.
5.10 MC68LC302 BUS INTERFACE SIGNAL SUMMARY
Table 5-3 and Table 5-4 summarize all bus signals discussed in the previous paragraphs.
They show the direction of each pin for the following bus masters: M68000 core, IDMA,
SDMA (includes DRAM refresh), and external bus masters. When the core is enabled, only
the LC302 core has access to the internal memory. When the core is disabled, the IDMA,
SDMA, and external bus masters can access either internal dual-port RAM and registers or
an external device or memory. When an external bus master accesses the internal dual-port
RAM or registers, the access may be synchronous or asynchronous.
External masters are only directly supported in the Disable CPU mode. When the core is
enabled and an external bus master needs the bus, then the HALT pin must be asserted to
the LC302 to halt the part.
5-12
MC68LC302 REFERENCE MANUAL
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