MC68LC302 Datasheet, PDF (51/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
DNS—Done Not Synchronized (NOT USED)
BES—Bus Error Source
This bit indicates that the IDMA channel terminated with an error during the read cycle.
BED—Bus Error Destination
This bit indicates that the IDMA channel terminated with an error during the write cycle.
DONE—Normal Channel Transfer Done
This bit indicates that the IDMA channel has terminated normally.
3.5 INTERRUPT CONTROLLER
The IMP interrupt controller accepts and prioritizes both internal and external interrupt re-
quests and generates a vector number during the CPU interrupt acknowledge cycle.
3.5.1 Interrupt Controller Key Differences
Since the function code pins are not connected externally, the MC68LC302 (with the core
enabled) should be programmed to Dedicated Mode and to internally generate the vectors
for Levels 1, 6, and 7. An external device will not be able to decode an IACK cycle and pro-
vide an vector back to the MC68LC302.
In Disable CPU mode, the IRQ1, IRQ6, and IRQ7 become the BR, BGACK, and BG signals.
With the core disabled, the MC68LC302 will not be able to decode an external CPU’s inter-
rupt acknowledge cycle. The user must poll the Interrupt Pending Register (IPR) during in-
terrupt handling to determine which peripheral caused the interrupt.
3.5.2 Interrupt Controller Programming Model
The user communicates with the interrupt controller using four registers. The global interrupt
mode register (GIMR) defines the interrupt controller's operational mode. The interrupt
pending register (IPR) indicates which INRQ interrupt sources require interrupt service. The
interrupt mask register (IMR) allows the user to prevent any of the INRQ interrupt sources
from generating an interrupt request. The interrupt in-service register (ISR) provides a ca-
pability for nesting INRQ interrupt requests.
3.5.2.1 Global Interrupt Mode Register (GIMR)
The user normally writes the GIMR soon after a total system reset. The GIMR is initially
$0000 and is reset only upon a total system reset.
15
14
13
12
11
10
9
8
7
5
4
0
MOD IV7
IV6
IV1
—
ET7 ET6 ET1
V7–V5
RESERVED
MOD—Mode (The Mode Should be set to Dedicated)
0 = Normal operational mode. Interrupt request lines are configured as IPL2–IPL0.
1 = Dedicated operational mode. Interrupt request lines are configured as IRQ7, IRQ6,
and IRQ1.
3-14
MC68LC302 REFERENCE MANUAL
MOTOROLA