MC68LC302 Datasheet, PDF (125/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.8 AC ELECTRICAL SPECIFICATIONS—IMP BUS MASTER CYCLES
(see Figure 6-2, Figure 6-3, and Figure 6-4)
Num.
Characteristic
16.67 MHz 20 MHz
25 MHz
@5.0 V
@5.0 V
@5.0 V
Symbol
Unit
Min Max Min Max Min Max
6 Clock High to FC, Address Valid
t_CHFCADV 0
45
0
45
0
30 ns
7
Clock High to Address, Data Bus High Im-
pedance (Maximum)
t_CHADZ
—
50
—
50
—
33
ns
8
Clock High to Address, FC Invalid (Mini-
mum)
t_CHAFI
0
—
0
—
0
— ns
9 Clock High to AS, DS Asserted (see Note 1) t_CHSL
3
30
3
30
3
20 ns
11
Address, FC Valid to AS, DS Asserted
(Read) AS Asserted Write (see Note 2)
t_AFCVSL 15 — 15 — 10 — ns
12 Clock Low to AS, DS Negated (see Note 1) t_CLSH — 30 — 30 — 20 ns
13
AS, DS Negated to Address, FC Invalid (see
Note 2)
t_SHAFI
15
—
15
—
10
—
ns
14
AS (and DS Read) Width Asserted (see
Note 2)
t_SL
120 — 120 — 80 — ns
14A DS Width Asserted, Write (see Note 2)
t_DSL
60 — 60 — 40 — ns
15 AS, DS Width Negated (see Note 2)
t_SH
60 — 60 — 40 — ns
16 Clock High to Control Bus High Impedance t_CHCZ — 50 — 50 — 33 ns
17 AS, DS Negated to R/W Invalid (see Note 2) t_SHRH 15 — 15 — 10 — ns
18 Clock High to R/W High (see Note 1)
t_CHRH — 30 — 30 — 20 ns
20 Clock High to R/W Low (see Note 1)
t_CHRL
— 30 — 30 — 20 ns
20A
AS Asserted to R/W Low (Write) (see Notes
2 and 6)
t_ASRV
— 10 — 10 —
7
ns
21
Address FC Valid to R/W Low (Write) (see
Note 2)
t_AFCVRL
15
—
15
—
10
—
ns
22
R/W Low to DS Asserted (Write) (see Note
2)
t_RLSL
30
—
30
—
20
— ns
23 Clock Low to Data-Out Valid
t_CLDO — 30 — 30 — 20 ns
25
AS, DS, Negated to Data-Out Invalid (Write)
(see Note 2)
t_SHDOI
15
—
15
—
10
—
ns
26
Data-Out Valid to DS Asserted (Write) (see
Note 2)
t_DOSL
15
—
15
—
10
—
ns
27
Data-In Valid to Clock Low (Setup Time on
Read) (see Note 5)
t_DICL
7 — 7 — 5 — ns
28
AS, DS Negated to DTACK Negated (Asyn-
chronous Hold) (see Note 2)
t_SHDAH
0 110 0 110 0
75 ns
29
AS, DS Negated to Data-In Invalid (Hold
Time on Read)
t_SHDII
0
—
0
— — — ns
31
DTACK Asserted to Data-In Valid (Setup
Time) (see Notes 2 and 5)
t_DALDI — 50 — 50 — 33 ns
32 HALT and RESET Input Transition Time t_RHr, t_RHf — 150 — 150 — 150 ns
44 AS, DS Negated to AVEC Negated
t_SHVPH
0
50
0
50
0
33 ns
47
Asynchronous Input Setup Time (see Note
5)
t_ASI
10 — 10 — 7 — ns
53 Data-Out Hold from Clock High
t_CHDOI
0
—
0
—
0
— ns
55
R/W Asserted to Data Bus Impedance
Change
t_RLDBD
0
—
0
—
0
— ns
6-8
MC68LC302 REFERENCE MANUAL
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