MC68LC302 Datasheet, PDF (136/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.11 AC ELECTRICAL SPECIFICATIONS—EXTERNAL MASTER
INTERNAL SYNCHRONOUS READ/WRITE CYCLES
Num.
(see Figure 6-9, Figure 6-10, and Figure 6-11)
16.67 MHz 20 MHz
25 MHz
Characteristic
Symbol _{Min Max Min Max Min Max} Unit
110 Address Valid to AS Low
t_AVASL 15 — 12 — 10 — ns
111 AS Low to Clock High
t_ASLCH 30 — 25 — 20 — ns
112 Clock Low to AS High
t_CLASH — 45 — 40 — 30 ns
113 AS High to Address Hold Time on Write
t_ASHAH
0—
0—
0 — ns
114 AS Inactive Time
t_ASH
1 — 1 — 1 — clk
115 UDS/LDS Low to Clock High (see Note 2) t_SLCH 40 — 33 — 27 — ns
116 Clock Low to UDS/LDS High
t_CLSH
— 45 —
40 — 30 ns
117 R/W Valid to Clock High (see Note 2)
t_RWVCH 30 — 25 — 20 — ns
118 Clock High to R/W High
t_CHRWH — 45 — 40 — 30 ns
119 AS Low to IAC High
t_ASLIAH — 40 — 35 — 27 ns
120 AS High to IAC Low
t_ASHIAL — 40 — 35 — 27 ns
121 AS Low to DTACK Low (0 Wait State)
t_ASLDTL — 45 — 40 — 30 ns
122 Clock Low to DTACK Low (1 Wait State) t_CLDTL — 30 — 25 — 20 ns
123 AS High to DTACK High
t_ASHDTH — 45 — 40 — 30 ns
124 DTACK High to DTACK High Impedance t_DTHDTZ — 15 — 15 — 10 ns
125 Clock High to Data-Out Valid
t_CHDOV — 30 — 25 — 20 ns
126 AS High to Data High Impedance
t_ASHDZ — 45 — 40 — 30 ns
127 AS High to Data-Out Hold Time
t_ASHDOI
0
—
0—
0 — ns
128 AS High to Address Hold Time on Read
t_ASHAI
0—
0—
0 — ns
129 UDS/LDS Inactive Time
t_SH
1 — 1 — 1 — clk
130 Data-In Valid to Clock Low
t_CLDIV 30 — 25 — 20 — ns
131 Clock Low to Data-In Hold Time
NOTES:
t_CLDIH 15 — 12 — 10 — ns
1. Synchronous specifications above are valid only when SAM = 1 in the SCR.
2. It is required that this signal not be asserted prior to the previous rising CLKO edge (i.e., in the previous
clock cycle). It must be recognized by the IMP no sooner than the rising CLKO edge shown in the
diagram.
MOTOROLA
MC68LC302 REFERENCE MANUAL
6-19