MC68LC302 Datasheet, PDF (105/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
WEL (LDS/DS)—Write Enable Low (Lower Data Strobe/Data Strobe)
When the core is enabled, this output pin functions as WEL and is active during a write
cycle to indicate that an external device should expect data on the D7-D0 of the data bus.
When the LC302 is in Disable CPU mode, this bidirectional line functions as LDS and con-
trols the flow of data on the data bus. When using a 16-bit data bus, this pin functions as
lower data strobe (LDS). When using an 8-bit data bus, this pin functions as DS. This line
is an output when the LC302 (M68000 core, SDMA or IDMA) is the bus master and is an
input otherwise.
DTACK—Data Transfer Acknowledge
This bidirectional signal indicates that the data transfer has been completed. DTACK can
be generated internally in the chip-select logic either for an LC302 bus master or for an
external bus master access to an external address within the chip-select ranges. It will
also be generated internally during any access to the on-chip dual-port RAM or internal
registers. If DTACK is generated internally, then it is an output. It is an input when the
LC302 accesses an external device not within the range of the chip-select logic or when
programmed to be generated externally.
IAC—Internal Access
The IAC signal is only available in the PGA package. This output indicates that the current
bus cycle accesses an on-chip location. This includes the on-chip 4K byte block of internal
RAM and registers (both real and reserved locations), and the system configuration reg-
isters ($0F0–$0FF). The above-mentioned bus cycle may originate from the M68000
core, the IDMA, or an external bus master. Note that, if the SDMA accesses the internal
dual-port RAM, it does so without arbitration on the M68000 bus; therefore, the IAC pin is
not asserted in this case. The timing of IAC is identical to that of the CS3–CS0 pins.
5.8 BUS ARBITRATION PINS
The bus arbitration pins are shown in Figure 5-7. These signals are only available in dis-
able CPU mode. When the core is enabled, the bus arbitration signals are the IPL2-0
signals.
BR
BGACK
BG
Figure 5-7. Bus Arbitration Pins
BR—Bus Request
This input signal indicates to the on-chip bus arbiter that an external device desires to be-
come the bus master.
5-10
MC68LC302 REFERENCE MANUAL
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