MC68LC302 Datasheet, PDF (21/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Configuration, Clocking, Low Power Modes, and Internal Memory Map
NOTE
It is not possible to start the system with PLL disabled and then
enable the PLL with software programming.
2.4.3 IMP System Clock Generation
2.4.3.1 SYSTEM CLOCK CONFIGURATION. The IMP has an on-chip oscillator and
phased locked loop (Figure 2-2). These features provide flexible ways to save power and
reduce system cost. The operation of the clock generation circuitry is determined by the fol-
lowing registers.
The IMP Operation Mode Control Register, IOMCR in 2.4.4.1.6 IMP Operation Mode Con-
trol Register (IOMCR).
The IMP PLL and Clock Control Register, IPLCR in A 32.768-kHz watch crystal provides
an inexpensive reference, but the EXTAL reference crystal frequency can be any frequency
from 25 kHz to 6.0 MHz. Additionally, the system clock frequency can be driven directly onto
the EXTAL pin. In this case, the EXTAL frequency should be the exact system frequency
desired (0 to Maximum Operating Frequency) and the XTAL pin should be left floating. Fig-
ure 2-4 shows all the external connections required for the on-chip oscillator (as well as the
PLL, VCC, and GND connection.
PIT
CLOCK
EXTAL
PIN
IMP
OSC.
XTAL
PIN
CLKIN
IMP SYSTEM CLOCK
(0 – MOF*)
DIVIDE
BY 2
BRG
CLOCK
MUX
* MOF is Maximum Operating Frequency
Figure 2-3. IMP System Clocks Schematic - PLL Disabled
Figure 2-2 shows the IMP system clocks schematic with the IMP PLL enabled. Figure 2-3
shows the IMP system clocks schematic with the IMP PLL disabled.
The clock generation features of the IMP are discussed in the following paragraphs.
2.4.3.2 ON-CHIP OSCILLATOR. A 32.768-kHz watch crystal provides an inexpensive ref-
erence, but the EXTAL reference crystal frequency can be any frequency from 25 kHz to 6.0
2-8
MC68LC302 REFERENCE MANUAL
MOTOROLA